Print board design assistance system, design assistance method, and recording medium

A design assistance method for selecting and determining a bypass capacitor to be mounted from among a plurality of bypass capacitors on a board on which a semiconductor integrated circuit device including a plurality of power supply terminals and a plurality of ground terminals is mounted, and on which the plurality of bypass capacitors each having a pair of electrodes is mountable, the design assistance method comprising:

• selecting a plurality of power supply terminals and a plurality of ground terminals of the semiconductor integrated circuit device to be mounted on the board and a plurality of bypass capacitors mountable on the board as a search target;
• calculating a shortest distance of a wiring path on the board corresponding to each of the plurality of bypass capacitors for each of the plurality of power supply terminals and the plurality of ground terminals of the semiconductor integrated circuit device selected;
• relatively comparing shortest distances of wiring paths on the board corresponding to each of the plurality of bypass capacitors calculated in each of the plurality of power supply terminals and the plurality of ground terminals of the semiconductor integrated circuit device, determining that a bypass capacitor whose shortest distance indicates a minimum value is valid, and determining that remaining bypass capacitors are invalid;
• and
• determining that a bypass capacitor determined to be valid in at least one of the plurality of power supply terminals and the plurality of ground terminals of the semiconductor integrated circuit device is valid for the board, and determining that other bypass capacitors are invalid for the board.

A non-transitory, tangible, computer readable recording medium storing a program for causing a computer to execute:

• selecting a plurality of power supply terminals and a plurality of ground terminals of a semiconductor integrated circuit device to be mounted on a board and a plurality of bypass capacitors mountable on the board as search targets;
• calculating a shortest distance of a wiring path on the board corresponding to each of the plurality of bypass capacitors for each of the plurality of power supply terminals and the plurality of ground terminals of the semiconductor integrated circuit device selected;
• relatively comparing the shortest distances of wiring paths on the board corresponding to each of the plurality of bypass capacitors calculated at each of the plurality of power supply terminals and the plurality of ground terminals of the semiconductor integrated circuit device, determining that a bypass capacitor whose shortest distance indicates a minimum value is valid, and determining that the remaining bypass capacitors are invalid;
• and
• determining that a bypass capacitor determined to be valid in at least one of the plurality of power supply terminals and the plurality of ground terminals of the semiconductor integrated circuit device is valid for the board and determining that other bypass capacitors are invalid for the board.

A design assistance system for selecting and determining a bypass capacitor to be mounted from among a plurality of bypass capacitors, the bypass capacitor being mounted on a board on which a semiconductor integrated circuit device of a grid array package in which terminals including the plurality of power supply terminals and the plurality of ground terminals are arranged in a lattice pattern on a bottom surface, including a plurality of power supply terminals and a plurality of ground terminals is mounted, and the plurality of bypass capacitors each having a pair of electrodes is mountable, the board including a power supply wiring layer to which the plurality of power supply terminals is connected, a ground wiring layer to which the plurality of ground terminals is connected, in a mounting region of the semiconductor integrated circuit device on a front surface, a power supply side wiring layer to which one electrode of the plurality of bypass capacitors is connected, and a ground side wiring layer to which the other electrode of the plurality of bypass capacitors is connected, in a region where the mounting region of the semiconductor integrated circuit device is projected on a back surface, the design assistance system comprising:

• a processor;
• and
• a memory storing a program, upon executed by the processor, performing a process:
• to calculate, for all combinations of the plurality of power supply terminals of the semiconductor integrated circuit device and one electrode of the plurality of bypass capacitors, a shortest distance in a wiring path from a connection position of the power supply wiring layer to which each of the plurality of power supply terminals of the semiconductor integrated circuit device is connected to each of connection positions of the power supply side wiring layer to which the one electrode of the plurality of bypass capacitors is connected;
• and
• to relatively compare shortest distances of wiring paths on the board corresponding to each of the plurality of bypass capacitors calculated in each of the plurality of power supply terminals of the semiconductor integrated circuit device, determine that a bypass capacitor connected to a wiring path whose shortest distance indicates a minimum value is valid, determine that remaining bypass capacitors are invalid, determine that the bypass capacitor determined to be valid among the plurality of bypass capacitors is valid for the board, determine that other bypass capacitors are invalid for the board, determines that, regarding the bypass capacitor determined to be valid for the board, a group A of bypass capacitors determined to be valid for the board is highly valid with respect to a group B determined to be invalid for the board, extracts adjacent power supply terminals with respect to the power supply terminals for the bypass capacitors belonging to the group A, selects one bypass capacitor from among the bypass capacitors for the extracted adjacent power supply terminals and leaves the selected bypass capacitor in the group A by relatively comparing shortest distances of wiring paths on the board corresponding to respective bypass capacitors for the extracted adjacent power supply terminals, and changes unselected bypass capacitor from the group A to the group B.