Automatic compilation method and framework for generating a layout of integrated memory-compute circuit

An automatic compilation framework for generating a layout for an integrated memory-compute circuit design, the framework comprising:

• a database constructed with at least one basic design library and a collection of referencing architecture templates;
• an automatic layout generator comprising:
• an architecture generator configured to:
• receive a user specification associated with the integrated memory-compute circuit design;
• select a referencing architecture template from the design database and parameterize the selected architecture template according to the received user specification to generate an architecture for the integrated memory-compute circuit design;
• and
• a placement & routing processor configured to:
• generate a physical layout based on the generated architecture according to one or more placement-and-routing algorithms;
• a design explorer configured to iterate a design exploration loop on the generated layout with one or more expertise experience-based optimization schemes to obtain one or more explored physical layouts;
• and
• a hardware performance evaluator configured to evaluate hardware metrics of the one or more explored physical layouts under one or more constraint conditions to determine an optimal physical layout.