Hybrid device with trusted execution environment

A method of hardware-software hybrid device with trusted execution environment operation comprising:

• defining at least two virtual processing cells including a trusted processing cell and at least one non-trusted processing cells, the virtual processing cells running on a processor;
• defining at least two virtual memory cells corresponding to at least two areas of a physical memory device according to memory cell configurations stored in a memory isolation gateway;
• assigning one of the virtual memory cells to each of the virtual processing cells;
• monitoring the processor for attempts to access the virtual memory cells due to instructions from one of the virtual processing cells;
• checking via the memory isolation gateway to ensure that the virtual memory cell being accessed by the processor corresponds to the virtual memory cell assigned to the virtual processing cell which provided the instruction to the processor to access the virtual memory cell;
• permitting the processor to access the virtual memory cell if the virtual memory cell corresponds to the virtual processing cell which provided the instruction to the processor to access the virtual memory cell and returning to the monitoring step, otherwise proceeding to the next step;
• blocking via the memory isolation gateway the attempt to access the virtual memory cell and returning an error indicating that the attempt to access the memory was unsuccessful, and returning to the monitoring step.

A method of hardware-software hybrid cell switching comprising:

• defining at least two virtual processing cells including a trusted processing cell and at least one non-trusted processing cell, the new cell being selected from one of the virtual processing cells;
• defining at least two virtual memory cells corresponding to at least two areas of a physical memory device according to memory cell configurations stored in a memory isolation gateway;
• assigning one of the virtual memory cells to each of the virtual processing cells;
• monitoring the processor for attempts to access the virtual memory cells due to instructions from one of the virtual processing cells;
• checking via the memory isolation gateway to ensure that the virtual memory cell being accessed by the processor corresponds to the virtual memory cell assigned to the virtual processing cell which provided the instruction to the processor to access the virtual memory cell;
• permitting the processor to access the virtual memory cell if the virtual memory cell corresponds to the virtual processing cell which provided the instruction to the processor to access the virtual memory cell and returning to the monitoring step, otherwise proceeding to the next step;
• and
• blocking via the memory isolation gateway the attempt to access the virtual memory cell and returning an error indicating that the attempt to access the memory was unsuccessful;
• setting up a timer in a processor to trigger an interrupt;
• entering an interrupt handler running in a trusted processing cell;
• setting a code register to a location of cell code;
• setting a new cell register to the location of a selected new cell;
• setting a cache purge flag to true;
• executing a cache purging operation with a cache purging controller;
• setting the cache purge flag to false;
• defining a memory clean-up starting address and a memory clean-up ending address to define a memory clean-up range;
• setting a memory clean-up flag to true;
• performing a memory clean-up operation on the memory clean-up range with a memory clean-up;
• performing cell switching functions including system services, inter-cell communication and checking cell pending events;
• executing a memory return instruction to the selected new cell;
• and,
• executing the instructions provided by the selected new cell.