Processor, method for executing an instruction on a processor, and computer

A processor, comprising at least one single-instruction multiple-thread processing unit, which includes:

• a plurality of warps for executing an instruction;
• a shared register group, which includes a plurality of general-purpose registers shared by the plurality of warps;
• and
• a predicate base address register, which is configured to:
• correspond to the plurality of warps;
• and
• indicate a base address for a subset of the plurality of general-purpose registers that serves as a predicate register for the warp in the shared register group, wherein:
• the warp performs a predicated execution for an instruction in view of a predicate value in the subset of the plurality of general-purpose registers that serves as the predicate register for the warp.

A method for executing an instruction on a processor, wherein:

• the processor includes:
• a plurality of warps for executing an instruction;
• a shared register group, which includes a plurality of general-purpose registers shared by the plurality of warps;
• and
• a predicate base address register, which is configured to:
• correspond to the plurality of the warps;
• and
• indicate a base address for a subset of the plurality of general-purpose registers that serves as a predicate register for the warp in the shared register group;
• and
• the method comprises the steps of:
• S1) transcoding a target instruction executed by the warp to obtain a predicate register in the target instruction;
• S2) obtaining a physical address of the predicate register specified in the target instruction in view of a base address of the subset of the plurality of general-purpose registers that serves as the predicate register for the warp indicated by the predicate base address register;
• S3) obtaining a predicate value in the predicate register specified in the target instruction in view of the physical address of the predicate register specified in the target instruction;
• and
• S4) performing a predicated execution for the target instruction in view of the predicate value in the predicate register specified in the target instruction.

A computer, comprising a processor, wherein:

• the processor includes at least one single-instruction multiple-thread processing unit;
• the single-instruction multiple-thread processing unit includes:
• a plurality of warps for executing an instruction;
• a shared register group, which includes a plurality of general-purpose registers shared by the plurality of warps;
• and
• a predicate base address register, which is configured to:
• correspond to the plurality of warps;
• and
• indicate a base address for a subset of the plurality of general-purpose registers that serves as a predicate register for the warp in the shared register group;
• and
• the warp performs a predicated execution for an instruction in view of a predicate value in the subset of the plurality of general-purpose registers that serves as the predicate register for the warp.