Boot and initialization techniques for stacked memory architectures

An apparatus, comprising:

• a first semiconductor die of a memory system, the first semiconductor die comprising:
• a common logic block;
• and
• a plurality of first interface blocks coupled with the common logic block;
• and
• one or more second semiconductor dies of the memory system coupled with the first semiconductor die and comprising:
• a plurality of second interface blocks, each second interface block coupled with a respective one of the plurality of first interface blocks via a respective set of one or more channels;
• and
• a plurality of memory arrays, each memory array coupled with one of the plurality of second interface blocks,
• wherein the common logic block comprises logic circuitry operable to initiate an initialization of the plurality of first interface blocks.

A method, comprising:

• receiving an evaluation command at a common logic block of a first semiconductor die of a memory system, the common logic block coupled with a plurality of interface blocks of the first semiconductor die that are each operable to access, via a respective set of one or more channels, one or more respective memory arrays of one or more second semiconductor dies of the memory system;
• outputting, based on receiving the evaluation command, an indication of an evaluation operation to each interface block of the plurality of interface blocks, the evaluation operation associated with evaluating access operations associated with the one or more respective memory arrays;
• receiving, by each interface block of the plurality of interface blocks, instructions for the evaluation operation based on the indication;
• and
• initiating a portion of the evaluation operation by each interface block of the plurality of interface blocks based on receiving the instructions.