Multi-port media access channel (mac) with flexible data-path width

Integrated circuitry comprising:

• receive datapath circuitry that is configurable to implement multiple receive datapath configurations between, at least in part, receive Media Access Control (MAC) layer processing circuitry and receive PHY layer processing circuitry, the multiple receive datapath configurations being mutually different from each other, at least in part;
• and
• configuration selection circuitry to generate one or more input signals to be provided to the receive datapath circuitry to select which of the multiple receive datapath configurations the receive datapath circuitry is to implement;
• wherein:
• the multiple receive datapath configurations are associated with respective datapath widths, respective supported link speeds, and respective supported lane configurations;
• the respective datapath widths comprise an 8 byte datapath width;
• the respective supported link speeds comprise 100 gigabit (Gb)/second(s), 200 Gb/s, 400 Gb/s, and one or more other link speeds;
• and
• the respective supported lane configurations comprise 1 lane/link, 2 lanes/link, 4 lanes/link, and at least one other number of lanes/link.

At least one non-transitory machine-readable storage medium storing instructions for being executed by at least one machine, the at least one machine to be associated with integrated circuitry, the instructions, when executed by the at least one machine, resulting in the integrated circuitry being configured for performance of operations comprising:

• generating, by configuration selection circuitry, one or more input signals to be provided to receive datapath circuitry, the receive datapath circuitry being configurable to implement multiple receive datapath configurations between, at least in part, receive Media Access Control (MAC) layer processing circuitry and receive PHY layer processing circuitry, the multiple receive datapath configurations being mutually different from each other, at least in part, the one or more input signals to be provided to the receive datapath circuitry to select which of the multiple receive datapath configurations the receive datapath circuitry is to implement;
• wherein:
• the multiple receive datapath configurations are associated with respective datapath widths, respective supported link speeds, and respective supported lane configurations;
• the respective datapath widths comprise an 8 byte datapath width;
• the respective supported link speeds comprise 100 gigabit (Gb)/second(s), 200 Gb/s, 400 Gb/s, and one or more other link speeds;
• and
• the respective supported lane configurations comprise 1 lane/link, 2 lanes/link, 4 lanes/link, and at least one other number of lanes/link.

A method implemented using integrated circuitry, the integrated circuitry comprising configuration selection circuitry and receive datapath circuitry, the method comprising:

• generating, by the configuration selection circuitry, one or more input signals to be provided to the receive datapath circuitry, the receive datapath circuitry being configurable to implement multiple receive datapath configurations between, at least in part, receive Media Access Control (MAC) layer processing circuitry and receive PHY layer processing circuitry, the multiple receive datapath configurations being mutually different from each other, at least in part, the one or more input signals to be provided to the receive datapath circuitry to select which of the multiple receive datapath configurations the receive datapath circuitry is to implement;
• wherein:
• the multiple receive datapath configurations are associated with respective datapath widths, respective supported link speeds, and respective supported lane configurations;
• the respective datapath widths comprise an 8 byte datapath width;
• the respective supported link speeds comprise 100 gigabit (Gb)/second(s), 200 Gb/s, 400 Gb/s, and one or more other link speeds;
• and
• the respective supported lane configurations comprise 1 lane/link, 2 lanes/link, 4 lanes/link, and at least one other number of lanes/link.

Integrated circuitry comprising:

• transmit datapath circuitry that is configurable to implement multiple transmit datapath configurations between, at least in part, transmit Media Access Control (MAC) layer processing circuitry and transmit PHY layer processing circuitry, the multiple transmit datapath configurations being mutually different from each other, at least in part;
• and
• configuration selection circuitry to generate one or more input signals to be provided to the transmit datapath circuitry to select which of the multiple transmit datapath configurations the transmit datapath circuitry is to implement;
• wherein:
• the multiple transmit datapath configurations are associated with respective datapath widths, respective supported link speeds, and respective supported lane configurations;
• the respective datapath widths comprise an 8 byte datapath width;
• the respective supported link speeds comprise 100 gigabit (Gb)/second(s), 200 Gb/s, 400 Gb/s, and one or more other link speeds;
• and
• the respective supported lane configurations comprise 1 lane/link, 2 lanes/link, 4 lanes/link, and at least one other number of lanes/link.

At least one non-transitory machine-readable storage medium storing instructions for being executed by at least one machine, the at least one machine to be associated with integrated circuitry, the instructions, when executed by the at least one machine, resulting in the integrated circuitry being configured for performance of operations comprising:

• generating, by configuration selection circuitry, one or more input signals to be provided to transmit datapath circuitry, the transmit datapath circuitry being configurable to implement multiple transmit datapath configurations between, at least in part, transmit Media Access Control (MAC) layer processing circuitry and transmit PHY layer processing circuitry, the multiple transmit datapath configurations being mutually different from each other, at least in part, the one or more input signals to be provided to the transmit datapath circuitry to select which of the multiple transmit datapath configurations the transmit datapath circuitry is to implement;
• wherein:
• the multiple transmit datapath configurations are associated with respective datapath widths, respective supported link speeds, and respective supported lane configurations;
• the respective datapath widths comprise an 8 byte datapath width;
• the respective supported link speeds comprise 100 gigabit (Gb)/second(s), 200 Gb/s, 400 Gb/s, and one or more other link speeds;
• and
• the respective supported lane configurations comprise 1 lane/link, 2 lanes/link, 4 lanes/link, and at least one other number of lanes/link.

A method implemented using integrated circuitry, the integrated circuitry comprising configuration selection circuitry and transmit datapath circuitry, the method comprising:

• generating, by the configuration selection circuitry, one or more input signals to be provided to the transmit datapath circuitry, the transmit datapath circuitry being configurable to implement multiple transmit datapath configurations between, at least in part, transmit Media Access Control (MAC) layer processing circuitry and transmit PHY layer processing circuitry, the multiple transmit datapath configurations being mutually different from each other, at least in part, the one or more input signals to be provided to the transmit datapath circuitry to select which of the multiple transmit datapath configurations the transmit datapath circuitry is to implement;
• wherein:
• the multiple transmit datapath configurations are associated with respective datapath widths, respective supported link speeds, and respective supported lane configurations;
• the respective datapath widths comprise an 8 byte datapath width;
• the respective supported link speeds comprise 100 gigabit (Gb)/second(s), 200 Gb/s, 400 Gb/s, and one or more other link speeds;
• and
• the respective supported lane configurations comprise 1 lane/link, 2 lanes/link, 4 lanes/link, and at least one other number of lanes/link.