Apparatuses and methods for controlling memory timing parameters

A memory circuit, comprising:

• a timing circuit configured to generate an internal clock signal having an internal clock frequency;
• a modulator configured to adjust a pulse width of the internal clock signal to generate a first clock signal having a first frequency, wherein the first frequency is a fraction of the internal clock frequency;
• and
• a memory controller configured to be:
• read via a first interface synchronized to the internal clock signal at the internal clock frequency;
• and
• programmed via a second interface synchronized to the first clock signal at the first frequency.

A method of operating a memory controller, comprising:

• generating a first clock signal having a first frequency;
• generating a second clock signal having a second frequency, wherein the second frequency is a fraction of the first frequency;
• and
• reading memory of the memory controller via a first interface synchronized to the first clock signal at the first frequency;
• or
• programming the memory of the memory controller via a second interface synchronized to the second clock signal at the second frequency.