Nic line-rate hardware packet processing

A packet engine located on a network interface card (NIC) for processing packets, comprising:

• a first match-action table comprising a plurality of match-action entries;
• a lookup logic to perform a lookup operation in the first match-action table based on a header of a received packet;
• an instruction memory to store a result of the lookup operation indicating an action to be performed on the received packet;
• a queuing logic to queue the received packet in a first queue in response to the lookup logic finding a match-action entry corresponding to the header of the received packet and to queue the received packet in both the first queue and a second queue in response to the lookup logic not finding the match-action entry;
• an arbiter to select, from a plurality of queues comprising the first queue and the second queue, a packet for processing;
• a packet-processing logic to:
• perform, on a first packet selected from the first queue, a corresponding action based on data stored in the instruction memory;
• and
• forward at least a portion of a second packet selected from the second queue to a processor coupled to the NIC to allow the processor to perform a second lookup operation in a second match-action table;
• and
• a receiving logic to receive, from the processor, a lookup result of the second lookup operation indicating an action to be performed on the second packet, thereby allowing a third packet in the first queue and corresponding to the second packet to be processed based on the lookup result.