Arithmetic unit for reduced instruction set computer processors and related method, system and device

A system, comprising:

• a memory;
• and
• a processor coupled to the memory, wherein the processor, in operation, executes an instruction set having a word size, the processor including arithmetic processing circuitry, which, in operation, executes arithmetic operations on operands having the word size, the arithmetic processing circuitry including:
• at least one arithmetic logic circuit (ALU) having an operand size smaller than the word size of the instruction set, wherein the at least one ALU, in operation, generates partial results of the arithmetic operations in a clock cycle;
• a multiplexing network coupled to inputs of the at least one ALU, wherein the multiplexing network, in operation, provides portions of the operands to the at least one ALU in a clock cycle;
• and
• a shift register having the word size of the instruction set and coupled to an output of the at least one ALU, wherein the shift register, in operation, accumulates partial results generated by at least one ALU over a plurality of clock cycles and outputs results of the arithmetic operations based on the accumulated partial results.

A method, comprising:

• executing, on a processor having an instruction set having a word size, an arithmetic operation on operands having the word size, the executing the arithmetic operation including:
• providing, using a multiplexing network of the processor, portions of the operands of the arithmetic operation to an arithmetic logic circuit (ALU) of the processor, the ALU having an operand size smaller than the word size of instruction set;
• generating, using the ALU, partial results of the arithmetic operation;
• accumulating, using a shift register of the processor, the shift register having the word size and coupled to an output of the at least one ALU, the partial results generated by the ALU;
• and
• generating a result of the arithmetic operation based on the accumulated partial results.

A non-transitory computer-readable medium having contents which configure a processor having an instruction set having a word size to perform a method, the method comprising:

• executing an arithmetic operation on operands having the word size of the instruction set, the executing the arithmetic operation including:
• providing, using a multiplexing network of the processor, portions of the operands of the arithmetic operation to an arithmetic logic circuit (ALU) of the processor, the ALU having an operand size smaller than the word size of instruction set;
• generating, using the ALU, partial results of the arithmetic operation;
• accumulating, using a shift register of the processor, the shift register having the word size, the partial results generated by the ALU;
• and
• generating a result of the arithmetic operation based on the accumulated partial results.