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US 2024/0393952 A1Published application
Memory device with a multiplexer circuit and multiple input/output interfaces
AssigneeMicron Technology, Inc.
InventorsChang H. Siau, Jonathan S. Parry
Life of this patent
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Abstract
A memory device including a first plane group, a second plane group and a multiplexer circuit. The multiplexer circuit is coupled to a first input/output (I/O) interface and a second I/O interface. The multiplexer circuit enables the first I/O interface to access the first plane group and the second plane group and enables the second I/O interface to access the first plane group and the second plane group.
Claims20
A memory device comprising:
- a first plane group and a second plane group;
- and
- a multiplexer circuit coupled to a first input/output (I/O) interface and a second I/O interface, the multiplexer circuit to perform operations comprising:
- enabling the first I/O interface to access the first plane group and the second plane group, and
- enabling the second I/O interface to access the first plane group and the second plane group.
2 more elements
A method comprising:
- enabling, by a multiplexer circuit coupled to a first input/output (I/O) interface and a second I/O interface of a memory device, the first I/O interface to access a first plane group and a second plane group of the memory device;
- and
- enabling, by the multiplexer circuit, the second I/O interface to access the first plane group and the second plane group of the memory device.
A memory sub-system comprising:
- a first memory device comprising a first plane group, a second plane group, a multiplexer circuit, a first I/O interface and a second I/O interface;
- and
- control logic, operatively coupled with the first I/O interface via a first channel and the second I/O interface via a second channel, to perform one or more operations comprising:
- transmitting, via the first channel to the first I/O interface, a first command to execute a first memory access operation associated with the first plane group, wherein the multiplexer circuit enables the first I/O interface to access the first plane group and the second plane group.
1 more element
Dependencies are inferred from the claim text.