Bipolar junction transistor (bjt) and fabricating method thereof

A method for fabricating a bipolar junction transistor (BJT), comprising:

• forming a collector region within a semiconductor substrate;
• forming a shallow trench isolation (STI) region within the collector region;
• forming a plurality of base regions over a first area of the collector region, wherein the first area of the collector region is surrounded by an inner side wall of the STI region;
• forming a plurality of emitter regions over the base regions;
• forming a base dielectric layer over the collector region and on opposite sides of the base regions;
• forming a base conductive layer over the base dielectric layer, wherein the base conductive layer is on the opposite sides of the base regions;
• and
• forming a plurality of base contacts over the base conductive layer,
• wherein the first area of the collector region is 3 to 8 times larger than a second area of the emitter regions projected onto the first area of the collector region,
• wherein the base contacts are divided into a first group of base contacts disposed between the base regions and a second group of base contacts disposed between the base regions and the STI region,
• wherein the first group of base contacts is formed over the first area of the collector region.

A method for fabricating a bipolar junction transistor (BJT), comprising:

• forming a collector region within a semiconductor substrate;
• forming a shallow trench isolation (STI) region within the collector region;
• forming a plurality of base regions over the collector region;
• forming a plurality of base dielectric layers over the collector region and on opposite sides of the base regions;
• forming a plurality of base conductive layers over and in contact with the base dielectric layers and on the opposite sides of the base regions, wherein the base conductive layers are in contact with sidewalls and top surfaces of the base regions;
• forming a plurality of emitter regions over the base regions;
• forming a plurality of spacer layers along vertical sidewalls of the emitter regions, wherein the spacer layers electrically isolate the emitter regions from the base conductive layers;
• and
• forming a plurality of base contacts over the base conductive layers,
• wherein the base regions are surrounded by an inner side of the STI region,
• wherein the base contacts are divided into a first group of base contacts disposed between the base regions and a second group of base contacts disposed between the base regions and the STI region.