Method of fabricating super-junction based vertical gallium nitride jfet and mosfet power devices

A vertical metal oxide semiconductor field effect transistor (MOSFET) device comprising:

• a substrate characterized by a first conductivity type;
• a first III-nitride layer coupled to the substrate, wherein the first III-nitride layer is characterized by a first dopant concentration and the first conductivity type;
• first trenches within the first III-nitride layer;
• a second III-nitride structure formed within the first trenches, wherein the second III-nitride structure is characterized by a second dopant concentration and a second conductivity type opposite to the first conductivity type;
• a third III-nitride layer coupled to the first III-nitride layer and the second III-nitride structure, wherein the third III-nitride layer is characterized by the second conductivity type;
• a fourth III-nitride layer coupled to the third III-nitride layer, wherein the fourth III-nitride layer is characterized by the first conductivity type;
• second trenches within the third III-nitride layer and the fourth III-nitride layer, wherein the second trenches expose a first portion of the first III-nitride layer;
• a gate dielectric within the second trenches, wherein the gate dielectric is coupled to the fourth III-nitride layer, the third III-nitride layer, and the first portion of the first III-nitride layer;
• a gate conductor within the second trenches, wherein the gate conductor is adjacent to the gate dielectric;
• and
• a source conductor coupled to an upper portion of the fourth III-nitride layer,
• wherein:
• the second dopant concentration is substantially equal to the first dopant concentration to provide a charge balance structure.

A method for fabricating a vertical metal oxide semiconductor field effect transistor (MOSFET) device comprising:

• providing a substrate characterized by a first conductivity type;
• providing a first III-nitride layer coupled to the substrate, wherein the first III-nitride layer is characterized by a first dopant concentration and the first conductivity type;
• providing first trenches within the first III-nitride layer;
• providing a second III-nitride structure formed within the first trenches, wherein the second III-nitride structure is characterized by a second dopant concentration and a second conductivity type opposite to the first conductivity type, wherein the second dopant concentration is substantially equal to the first dopant concentration;
• providing a third III-nitride layer coupled to the first III-nitride layer and the second III-nitride structure, wherein the third III-nitride layer is characterized by the second conductivity type;
• providing a fourth III-nitride layer coupled to the third III-nitride layer, wherein the fourth III-nitride layer is characterized by the first conductivity type;
• providing second trenches within the third III-nitride layer and the fourth III-nitride layer, wherein the second trenches expose a first portion of the first III-nitride layer;
• providing a gate dielectric within the second trenches, wherein the gate dielectric is coupled to the fourth III-nitride layer, the third III-nitride layer, and the first portion of the first III-nitride layer;
• providing a gate conductor within the second trenches, wherein the gate conductor is adjacent to the gate dielectric;
• and
• providing a source conductor coupled to an upper portion of the fourth III-nitride layer.