Dielectric sidewall structure for quality improvement in ge and sige devices

An integrated circuit (IC), comprising:

• a substrate comprising a well region;
• a dielectric layer arranged over a topmost surface of the substrate and overlying outer edges of the well region, wherein the dielectric layer has inner sidewalls surrounding an opening in the dielectric layer;
• an epitaxial pillar of SiGe or Ge extending upward from the well region within the opening and having a bottommost surface that contacts the dielectric layer;
• and
• a dielectric sidewall structure surrounding the epitaxial pillar and having both a bottom surface that rests on an upper surface of the dielectric layer and inner sidewalls that contact the inner sidewalls of the dielectric layer.

An integrated circuit (IC), comprising:

• a substrate comprising a well region;
• a first dielectric layer arranged over a topmost surface of the substrate and overlying outer edges of the well region, wherein the first dielectric layer has inner sidewalls surrounding an opening in the first dielectric layer;
• an epitaxial pillar of SiGe or Ge extending upward from the well region within the opening and having a bottommost surface that contacts the first dielectric layer;
• a second dielectric layer overlying the first dielectric layer, the second dielectric layer comprising inner sidewalls surrounding the opening in the first dielectric layer and offset from the inner sidewalls of the first dielectric layer by a first distance;
• and
• a dielectric sidewall structure surrounding the epitaxial pillar and having a width substantially equal to the first distance.