Low capacitance poly-bounded silicon controlled rectifiers

A semiconductor die comprising:

• a plurality of pads including a signal pad and a ground pad;
• a circuit electrically connected to the signal pad;
• and
• a silicon controlled rectifier (SCR) including an anode terminal electrical connected to the signal pad and a cathode terminal electrically connected to the ground pad, wherein the SCR comprises:
• an n-type well (NW) formed in a substrate;
• a p-type well (PW) formed in the substrate adjacent to the NW;
• a plurality of active regions including a first p-type active (P+) fin region over the NW and connected to the anode terminal, and a first n-type active (N+) fin region over the PW and connected to the cathode terminal;
• and
• a plurality of polysilicon gate regions formed over the PW and NW, wherein the plurality of polysilicon gate regions separate the plurality of active regions.

A method of forming a silicon controlled rectifier (SCR) protection structure, the method comprising:

• forming an n-type well (NW) in a substrate;
• forming a p-type well (PW) formed in the substrate adjacent to the NW;
• forming a plurality of active regions over the PW and the NW, wherein the plurality of active regions include a first p-type active (P+) fin region over the NW and serving as an anode of the SCR, and a first n-type active (N+) fin region over the PW and serving as a cathode of the SCR;
• and
• separating the plurality of active regions by forming a plurality of polysilicon gate regions over the PW and NW.