Memory device and manufacturing method of the same
AssigneeIpcell Corporation Limited
InventorTe-Hsun HSU
Life of this patent
Estimating the term…
Abstract
The present disclosure relates to a memory device including a gate erased region and a floating gate transistor. The erased gate region includes a first well. The floating gate transistor includes a first channel area and a second channel area that are arranged in a first direction and a floating gate structure arranged above the first channel area and the second channel area. The floating gate structure extends over the first well in a second direction. The first channel region and the second channel region have different channel formation critical voltages. With the memory device provided by the present disclosure, the erase voltage applied to the erased gate region is reduced to prevent the semiconductor junction from collapsing, thereby improving the reliability of the memory device.
Claims20
A memory device, comprising:
- a first well;
- a first doped region disposed in the first well and coupled to an erasure signal line, and the first doped region having a first conducting type;
- a second doped region disposed in a second well and coupled to a bit line, and the second doped region having a second conducting type;
- and
- a floating gate structure crossing above the first well and the second well, and the floating gate structure comprising:
- a first gate structure having a first capacitive coupling ratio and a second gate structure, wherein the first gate structure and the second gate structure are disposed above the second well, and the second gate structure has a second capacitive coupling ratio different from the first capacitive coupling ratio.
A memory device, comprising:
- an erasure gate region comprising:
- a first well;
- and
- a floating gate transistor comprising:
- a first channel region and a second channel region that are disposed along a first direction;
- and
- a floating gate structure disposed above the first channel region and the second channel region, and the floating gate structure extending above the first well along a second direction different from the first direction, wherein the first channel region and the second channel region have different critical voltages of channel formation.
A manufacturing method of a memory device, comprising following steps:
- forming a first doped region in a first well;
- forming a gate dielectric layer extending along a first direction on the first well and a second well, wherein the gate dielectric layer covers a first channel region and a second channel region that are disposed along a second direction which is different from the first direction;
- and
- forming a floating gate structure on the gate dielectric layer, wherein the floating gate structure comprises:
- in a planar view, a first portion overlapping the first channel region and a second portion overlapping the second channel region, and the first channel region being between the first doped region and the second channel region in the planar view, wherein a first capacitive coupling ratio of the first portion to the first doped region is different from a second capacitive coupling ratio of the second portion to the first well.
Dependencies are inferred from the claim text.