US 2024/0357805 A1 · MEMORY DEVICE, INTEGRATED CIRCUIT AND MANUFACTURING METHOD OF THE SAME

Abstract

A memory device comprises a memory cell comprising first to third transistors and a fuse element. A control terminal and a first terminal of the first transistor are coupled to a write word line and a source line respectively. The second transistor has a control terminal coupled to a second terminal of the first transistor and a first terminal coupled to a bit line. A first terminal of the fuse element is coupled to the second terminal of the first transistor and the control terminal of the second transistor. A control terminal of the third transistor is coupled to a read word line. First and second terminals of the third transistor are coupled to the source line and a second terminal of the second transistor. The first transistor is turned on to form a write path and the second and third transistors form a read path.

Claims20

Dependent claims

A memory device comprising a one-time programmable non-volatile memory cell that comprises:

a first transistor, a control terminal of the first transistor and a first terminal of the first transistor coupled to a write word line and a source line respectively;
a second transistor that has a control terminal coupled to a second terminal of the first transistor and has a first terminal coupled to a bit line;
a fuse element, wherein a first terminal of the fuse element is coupled to the second terminal of the first transistor and the control terminal of the second transistor;
and
a third transistor, wherein a control terminal of the third transistor is coupled to a read word line, a first terminal of the third transistor is coupled to the source line and a second terminal of the third transistor is coupled to a second terminal of the second transistor,
wherein the first transistor is configured to be turned on to form a write path to the fuse element, and the second transistor and the third transistor are configured as a read path.

3 more elements

A manufacturing method of integrated circuit comprising the following steps:

forming a first active region and a second active region that are separated from each other along a first direction in a substrate;
forming a first gate structure extending along the first direction, wherein forming the first gate structure comprising:
forming a first gate portion of the first gate structure on a shallow trench isolation and forming a second gate portion overlapping the first gate structure of the first active region in a layout view;
and
forming a first conductive structure and a second conductive structure that contact the first gate portion, the first conductive structure coupled to the second active region, wherein an area of the first conductive structure is larger than an area of the second conductive structure.

2 more elements

Dependencies are inferred from the claim text.

Memory device, integrated circuit and manufacturing method of the same

Life of this patent

Memory device, integrated circuit and manufacturing method of the same

Life of this patent

Abstract

Claims20