Microprocessor with floating-point cordic instructions

A processor comprising:

• a central processing unit (CPU);
• and
• a digital signal processing (DSP) circuit coupled to the CPU, wherein the CPU and DSP circuit are integrated in a same semiconductor die, wherein the DSP circuit comprises a floating-point CORDIC circuit for computing sine and cosine functions iteratively in multiple iterations, wherein the floating-point CORDIC circuit comprises:
• a counter configured to be incremented by one after each iteration;
• an angle updating circuit configured to be initialized with an initial value for an angle and configured to compute, for each iteration, an updated value for the angle based on a current value of the angle and a pre-determined rotation angle for each iteration;
• and
• a coordinate updating circuit comprising:
• a first register for storing a floating-point value corresponding to the cosine function;
• a second register for storing a floating-point value corresponding to the sine function;
• a first custom floating-point adder/subtractor circuit;
• and
• a second custom floating-point adder/subtractor circuit having a same structure as the first custom floating-point adder/subtractor circuit, wherein each of the first and the second custom floating-point adder/subtractor circuits has a first input terminal, a second input terminal, a third input terminal, and a fourth input terminal, wherein the first input terminal, the second input terminal, and the third input terminal of the first custom floating-point adder/subtractor circuit are coupled to an output terminal of the first register, an output terminal of the second register, and an output terminal of the counter, respectively, and wherein the first input terminal, the second input terminal, and the third input terminal of the second custom floating-point adder/subtractor circuit are coupled to the output terminal of the second register, the output terminal of the first register, and the output terminal of the counter, respectively.

An electrical system comprising:

• a processor comprising:
• a central processing unit (CPU);
• and
• a digital signal processing (DSP) circuit coupled to the CPU, wherein the CPU and DSP circuit are integrated in a same semiconductor die, wherein the DSP circuit comprises a floating-point CORDIC circuit configured to convert a vector in a polar coordinate system into coordinates in a Cartesian coordinate system by operating the floating-point CORDIC circuit in multiple iterations of operation, wherein the floating-point CORDIC circuit comprises:
• a counter configured to be incremented by one after each iteration;
• an angle updating circuit configured to be initialized with an initial value for an angle and configured to compute, for each iteration, an updated value for the angle based on a current value of the angle and a pre-determined rotation angle for each iteration;
• and
• a coordinate updating circuit comprising:
• a first register for storing a first floating-point value corresponding to an X-coordinate in the Cartesian coordinate system;
• a second register for storing a second floating-point value corresponding to a Y-coordinate in the Cartesian coordinate system;
• a first custom floating-point adder/subtractor circuit, wherein the first custom floating-point adder/subtractor circuit is configured to, for each iteration, calculate an updated value for the first floating-point value by computing a difference between the first floating-point value and a scaled version of the second floating-point value, wherein the scaled version of the second floating-point value is a product of a sign of the current value of the angle and the second floating-point value divided by 2i, wherein i is an output of the counter, wherein the first custom floating-point adder/subtractor circuit is configured to compute the second floating-point value divided by 2i by subtracting i from an exponent of the second floating-point value;
• and
• a second custom floating-point adder/subtractor circuit, wherein the second custom floating-point adder/subtractor circuit is configured to, for each iteration, calculate an updated value for the second floating-point value by computing a sum of the second floating-point value and a scaled version of the first floating-point value, wherein the scaled version of the first floating-point value is a product of the sign of the current value of the angle and the first floating-point value divided by 2i, wherein the second custom floating-point adder/subtractor circuit is configured to compute the first floating-point value divided by 2i by subtracting i from an exponent of the first floating-point value;
• a load coupled to the processor;
• a control path between the processor and load, wherein the control path is configured to send control signals from the processor to the load;
• and
• a feedback path between the load and the processor, wherein the feedback path is configured to send feedback signals from the load to the processor.