Memory device for signed multi-bit to multi-bit multiplications

Abstract

Systems, methods, and apparatus related to memory devices that perform signed multi-bit to multi-bit multiplication using sets of memory cells. In one approach, a memory cell array has sets of memory cells. Each set is programmable to store a multi-bit signed weight. Voltage drivers apply voltages to each set. The voltages correspond to multi-bit signed inputs. One or more common lines are coupled to each set for summing output currents from the sets during the multiplication. A digitizer provides signed results based on summing the output currents. The signed results are added with adjustment for the bit significance of each signed result to provide a final accumulation result for the multiplication.

Dependencies are inferred from the claim text.