Semiconductor device and electronic system including the same

A semiconductor device comprising:

• a first substrate;
• a circuit region including a peripheral circuit structure on the first substrate;
• and
• a cell region that is on the circuit region and includes a cell array region and a connection region,
• wherein the cell region includes:
• a second substrate;
• a gate stacking structure that is on the second substrate and includes a lower structure and an upper structure, wherein the lower structure and the upper structure each include a plurality of gate electrodes;
• a channel structure penetrating the gate stacking structure;
• a gate contact portion that penetrates the gate stacking structure to be electrically connected to the circuit region;
• and
• a boundary insulating pattern that is partially formed in a boundary gate electrode among the plurality of gate electrodes of the lower structure adjacent to a boundary portion between the upper structure and the lower structure to surround the gate contact portion to maintain an electrical connection path of the boundary gate electrode;
• and
• wherein an entire side surface of the boundary insulating pattern includes an inclined surface that gradually decreases in width toward the second substrate or a vertical surface perpendicular to the second substrate when the boundary insulating pattern is viewed in a cross-section.

An electronic system. comprising:

• a main substrate;
• a semiconductor device on the main substrate;
• and
• a controller electrically connected to the semiconductor device on the main substrate,
• wherein the semiconductor device includes a circuit region including a peripheral circuit structure on a first substrate and a cell region that is disposed on the circuit region and includes a cell array region and a connection region, and
• wherein the cell region includes:
• a second substrate;
• a gate stacking structure that is on the second substrate and includes a lower structure and an upper structure, wherein the lower structure and the upper structure each include a plurality of gate electrodes;
• a channel structure penetrating the gate stacking structure;
• a gate contact portion that penetrates the plurality of gate electrodes to be electrically connected to the circuit region, is electrically connected to a connection gate electrode among the plurality of gate electrodes, and is insulated from a remaining gate electrode by an insulating pattern that is disposed between the remaining gate electrode and the gate contact portion;
• and
• a boundary insulating pattern that is partially formed in a boundary gate electrode among the plurality of gate electrodes of the lower structure adjacent to a boundary portion between the upper structure and the lower structure to surround the gate contact portion to maintain an electrical connection path of the boundary gate electrode and has a different structure from that of the insulating pattern.