US 2024/0268111 A1 · THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF FORMING THE SAME

Abstract

Provided is a three-dimensional (3D) memory device including: a substrate, a stack structure, and a vertical channel pillar. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of gate layers stacked alternately. The vertical channel pillar penetrates through the stack structure. The vertical channel pillar includes a first source/drain pillar and a channel layer laterally surrounding the first source/drain pillar. The first source/drain pillar includes a first buffer pillar and a first semiconductor layer having a first conductivity type wrapping the first buffer pillar. The channel layer includes a polysilicon layer having a second conductivity type different from the first conductivity type. In some embodiments, the 3D memory device may be, but is not limited to, a AND flash memory.

Claims20

Dependent claims

A three-dimensional (3D) memory device, comprising:

a substrate;
a stack structure, disposed on the substrate, wherein the stack structure comprises a plurality of dielectric layers and a plurality of gate layers stacked alternately;
and
a vertical channel pillar, penetrating through the stack structure, wherein the vertical channel pillar comprises:
a first source/drain pillar comprising a first buffer pillar and a first semiconductor layer having a first conductivity type wrapping the first buffer pillar;
a second source/drain pillar comprising a second buffer pillar and a second semiconductor layer having the first conductivity type wrapping the second buffer pillar;
and
a channel layer laterally surrounding the first source/drain pillar and the second source/drain pillar, wherein the channel layer comprises a polysilicon layer having a second conductivity type different from the first conductivity type.

5 more elements

A method of forming a three-dimensional (3D) memory device, comprising:

forming a stop layer and a stack structure on a substrate, wherein the stack structure comprises a plurality of dielectric layers and a plurality of sacrificial layers stacked alternately;
forming a first opening in the stack structure and the stop layer;
forming a vertical channel pillar in the first opening, wherein the vertical channel pillar comprises:
a first source/drain pillar comprising a first buffer pillar and a first semiconductor layer having a first conductivity type wrapping the first buffer pillar;
and
a channel layer laterally surrounding the first source/drain pillar, wherein the channel layer comprises a polysilicon layer having a second conductivity type different from the first conductivity type;
and
performing a gate replacement process to replace the plurality of sacrificial layers by a plurality of gate layers.

5 more elements

Dependencies are inferred from the claim text.

Three-dimensional memory device and method of forming the same

Life of this patent

Three-dimensional memory device and method of forming the same

Life of this patent

Abstract

Claims20