Clock edge correcting device and operating method thereof

A method of correcting a clock, the method comprising:

• receiving a first clock, a second clock, a third clock, and a fourth clock;
• adjusting a phase of a second rising edge of the second clock based on a first rising edge of the first clock and on a third rising edge of the third clock;
• adjusting a phase of a fourth rising edge of the fourth clock based on the first rising edge and on the third rising edge after adjusting the phase of the second rising edge;
• adjusting a phase of the third rising edge based on the adjusted second rising edge and on the adjusted fourth rising edge after the phase adjustment of the fourth rising edge;
• adjusting a phase of a first falling edge of the first clock based on the first rising edge;
• adjusting a phase of a second falling edge of the second clock based on the first rising edge;
• adjusting a phase of a third falling edge of the third clock based on the first rising edge;
• adjusting a phase of a fourth falling edge of the fourth clock based on the first rising edge;
• and
• transmitting the adjusted first clock, the adjusted second clock, the adjusted third clock, and the adjusted fourth clock,
• wherein the adjusted first clock, the adjusted second clock, the adjusted third clock, and the adjusted fourth clock are quadrature with each other.

A clock correction circuit comprising:

• an edge corrector circuit configured to receive a first clock, a second clock, a third clock, and a fourth clock;
• a rising edge error detector circuit configured to detect errors of a second rising edge of the second clock, a third rising edge of the third clock, and a fourth rising edge of the fourth clock, the detecting based on the first rising edge of the first clock;
• and
• a falling edge error detector circuit configured to detect errors of each of the first falling edge of the first clock, the second falling edge of the second clock, the third falling edge of the third clock, and the fourth falling edge of the fourth clock, the detecting based on the first rising edge,
• wherein the edge corrector circuit is configured to
• correct each of the second rising edge, the third rising edge, and the fourth rising edge based on the error of each of a respective one of the second rising edge, the third rising edge, and the fourth rising edge,
• correct each of the first falling edge, the second falling edge, the third falling edge, and the fourth falling edge based on a respective one of the error of each of the first falling edge, the second falling edge, the third falling edge, and the fourth falling edge, and
• transmit the first clock based on the correction of the first falling edge, the second clock based on the correction of the second rising edge and the second falling edge, the third clock based on the correction of the third rising edge and the third falling edge, and the fourth clock based on the correction of the fourth rising edge and the fourth falling edge,
• wherein the first clock based on the correction, the second clock based on the correction, the third clock based on the correction, and the fourth clock based on the correction are quadrature with each other.