A trench SiC MOSFET integrated with a high-speed flyback diode, comprising a back ohmic contact alloy, an N-type doped SiC substrate, an N-type doped SiC epitaxial layer, a first P-type doped buried layer, a second P-type doped buried layer, a third P-type doped buried layer, a first gate oxide layer, a second gate oxide layer, a first polysilicon layer, a second polysilicon layer, a first P-type doped well region, a second P-type doped well region, a third P-type doped well region, a first N-type doped source region, a second N-type doped source region, a P-type doped source region, an inter-layer dielectric, and a front ohmic contact alloy;
- in a plane defined by an x-axis and a y-axis, the N-type doped SiC substrate is located over the back ohmic contact alloy, the N-type doped SiC epitaxial layer is located over the N-type doped SiC substrate, the second P-type doped buried layer is located over a right portion of the N-type doped SiC epitaxial layer, the third P-type doped buried layer is located over a left portion of the N-type doped SiC epitaxial layer, the first gate oxide layer is located over the second P-type doped buried layer, the second gate oxide layer is located over the third P-type doped buried layer, the first polysilicon layer is located over a right portion of the first gate oxide layer, the second polysilicon layer is located over a left portion of the second gate oxide layer, the first N-type doped source region is located over a left portion of the first gate oxide layer, the P-type doped source region is located on a left side of the first N-type doped source region, the second N-type doped source region is located on a left side of the P-type doped source region and is connected to a right side of the second gate oxide layer, the first P-type doped well region is located under the first N-type doped source region and on a left side of the first gate oxide layer, the second P-type doped well region is located under the first N-type doped source region, the P-type doped source region- and the second N-type doped source region and on a left side of the first N-type doped source region, the third P-type doped well region is located under the second N-type doped source region and on a left side of the second P-type doped well region, the inter-layer dielectric is located over the first N-type doped source region, the first gate oxide layer and the first polysilicon layer, and the front ohmic contact alloy is located over the inter-layer dielectric, the first N-type doped source region, the P-type doped source region, the second N-type doped source region, the second gate oxide layer, and the second polysilicon layer;
- in a plane defined by the y-axis and a z-axis, the N-type doped SiC substrate is located over the back ohmic contact alloy, the N-type doped SiC epitaxial layer is located over the N-type doped SiC substrate, the first P-type doped buried layer is located at an upper right position in the N-type doped SiC epitaxial layer, the second P-type doped buried layer is located at an upper left position in the N-type doped SiC epitaxial layer, the first gate oxide layer is located over the first P-type doped buried layer, the N-type doped SiC epitaxial layer and the second P-type doped buried layer, the first polysilicon layer is located over the first gate oxide layer, the inter-layer dielectric is located over the first polysilicon layer, and the front ohmic contact alloy is located over the inter-layer dielectric.