US 2024/0266398 A1Published application

Source/Drain Device and Method of Forming Thereof

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsChien-I Kuo, Wei Hao Lu, Li-Li Su, Yee-Chia Yeo

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Abstract

A method of forming a semiconductor includes forming a first recess in a first semiconductor fin protruding from a substrate and forming a second recess in a second semiconductor fin protruding from the substrate first semiconductor fin and forming a source/drain region in the first recess and the second recess. Forming the source/drain region includes forming a first portion of a first layer in the first recess and forming a second portion of the first layer in the second recess, forming a second layer on the first layer by flowing a first precursor, and forming a third layer on the second layer by flowing a second precursor, the third layer being a single continuous material.

Claims20

Dependent claims

A semiconductor device, comprising:

a first semiconductor fin and a second semiconductor fin, the first semiconductor fin and the second semiconductor fin extending from a substrate;
an isolation region disposed on the substrate between the first semiconductor fin and the second semiconductor fin;
and
a source/drain region over the first semiconductor fin and the second semiconductor fin, the source/drain region comprising:
a first layer, a first portion of the first layer extending from the first semiconductor fin, a second portion of the first layer extending from the second semiconductor fin;
a second layer, a first portion of the second layer extending from the first portion of the first layer, a second portion of the second layer extending from the second portion of the first layer;
and
a third layer, the third layer being a single continuous layer extending from the first portion of the second layer to the second portion of the second layer, the third layer having a first height in a range from 30 nm to 38 nm, the first height being measured as the shortest distance from a top surface of the isolation region to a merge point of the third layer, the merge point being a highest point of a bottom surface of the third layer between the first semiconductor fin and the second semiconductor fin.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/636,490Filed 16 Apr 2024
Priority: 27 Aug 2021
Published: 8 Aug 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10D 62/151
Source or drain regions of field-effect devices: of igfets
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/62
Insulated-gate field-effect transistors [IGFET]: fin field-effect transistors [FinFET]
H10D 30/6211
Fin field-effect transistors [FinFET]: having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates

Family

Application17/458,950Division · filed 27 Aug 2021
Application18/636,490Division
US 11,990,511 B2Related patent
US 12,349,426 B2Related patent
US 2023/0068434 A1Published application
US 2024/0266398 A1This patent

From the US filing history. Foreign family members aren’t listed.

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