Integrated circuit with and method for connection of a plurality of floating diffusion regions

A pixel element array comprising:

• an isolation region;
• a plurality of pixel elements adjoining the isolation region along different isolation region surfaces, each of the plurality of pixel elements comprising a respective floating diffusion region;
• a dielectric layer extending over the isolation region and having sidewalls forming openings over the respective floating diffusion region within the plurality of pixel elements;
• a conductive layer extending from over the dielectric layer to adjoin in direct and ohmic connection a respective first floating diffusion region surface of each respective floating diffusion region of each of the plurality of pixel elements;
• and
• a contact etch stop layer disposed over and along sidewalls of the conductive layer.

A method for manufacturing an integrated circuit, the method including:

• forming an isolation region in a substrate between a first semiconductor substrate region and a second semiconductor substrate region;
• forming a dielectric layer extending from over the isolation region to over the first semiconductor substrate region and the second semiconductor substrate region;
• patterning the dielectric layer to form openings exposing the first semiconductor substrate region and the second semiconductor substrate region;
• implanting the substrate according to the openings to form a first floating diffusion region in the first semiconductor substrate region and a second floating diffusion region in the second semiconductor substrate region;
• and
• forming a conductive layer over the dielectric layer and within the openings, the conductive layer being electrically connected to the first floating diffusion region and to the second floating diffusion region.