Semiconductor device and manufacturing method thereof

A semiconductor device comprising:

• a semiconductor substrate having a first main surface and a second main surface opposing the first main surface;
• a first semiconductor layer of a first conductivity type, the first semiconductor layer being provided on the first main surface of the semiconductor substrate;
• a second semiconductor layer provided on the first semiconductor layer and having a first portion of the first conductivity type and a second portion of a second conductivity type;
• a third semiconductor layer of the second conductivity type, the third semiconductor layer being provided on the second semiconductor layer;
• a power transistor provided in a power transistor region that is a part of a plan view layout on the first main surface of the semiconductor substrate;
• and
• a drive circuit of the power transistor provided in a CMOS region that is another part of the plan view layout of the semiconductor substrate, the drive circuit being configured by a p-type MOSFET and an n-type MOSFET,
• wherein the power transistor has:
• a power source region of the first conductivity type, the power source region being selectively provided in a portion of the third semiconductor;
• a trench groove penetrating through the power source region and the third semiconductor layer and having a depth reaching the second semiconductor layer;
• a trench gate electrode provided in the trench groove via a trench gate insulating film;
• a first source electrode connected to the power source region;
• and
• a first drain electrode provided on the second main surface,
• wherein the p-type MOSFET has:
• a first source region of the second conductivity type and a first drain region of the second conductivity type, the first source region and the first drain region being formed in a first well region of the first conductivity type, the first well region being provided in a part of the third semiconductor layer;
• a buried channel region of the second conductivity type, the buried channel region being provided between the first source region and the first drain region;
• and
• a first gate electrode provided over the buried channel region via a first gate insulating film,
• wherein the n-type MOSFET has:
• a second source region of the first conductivity type and a second drain region of the first conductivity type, the second source region and the second drain region being provided in a part of the third semiconductor layer;
• a channel region provided between the second source region and the second drain region;
• and
• a second gate electrode provided on the channel region via a second gate insulating film, and
• wherein an impurity concentration of the second conductivity type of the buried channel region is equal to an impurity concentration of the second conductivity type of the third semiconductor layer.