Standard cell layout methodology for low leakage solutions

A method, comprising:

• forming a first semiconductor track in an integrated circuit;
• forming a second semiconductor track in the integrated circuit;
• forming a first drain subregion and a first source subregion of a first transistor in the first semiconductor track;
• forming a second drain subregion and a second source subregion of the first transistor in the second semiconductor track;
• forming a first trench isolation region between the first semiconductor track and the second semiconductor track, wherein the first trench isolation region isolates the first drain subregion from the second drain subregion;
• and
• forming a diffusion bridge of semiconductor material connecting the first source subregion to the second source subregion.

An integrated circuit, comprising:

• a semiconductor substrate including:
• a first semiconductor track;
• a second semiconductor track separated from the first semiconductor track by a first trench isolation region;
• and
• a third semiconductor track separated from the second semiconductor track by a second trench isolation region;
• and
• a logic gate including:
• a first transistor having a first drain subregion in the first semiconductor track, a second drain subregion in the second semiconductor track, a first source subregion in the first semiconductor track and a second source subregion in the second semiconductor track, and a diffusion bridge of semiconductor material extending between the first source subregion and the second source subregion;
• and
• a second transistor having a source region and a drain region in the third semiconductor track.