Structure and formation method of package with integrated chips

A method for forming a package structure, comprising:

• providing a semiconductor wafer, wherein the semiconductor wafer has a front-side interconnection structure, a device portion, and a back-side interconnection structure, and the device portion is between the front-side interconnection structure and the back-side interconnection structure;
• performing a planarization process on one of the front-side interconnection structure and the back-side interconnection structure;
• and
• bonding a chip structure to one of the front-side interconnection structure and the back-side interconnection structure using dielectric-to-dielectric bonding and metal-to-metal bonding after the planarization process.

A package structure, comprising:

• a first chip structure, wherein the first chip structure has a front-side interconnection structure, a device portion, and a back-side interconnection structure, and the device portion is between the front-side interconnection structure and the back-side interconnection structure;
• a stack of conductive vias formed in the back-side interconnection structure;
• and
• a second chip structure directly bonded to one of the front-side interconnection structure and the back-side interconnection structure using dielectric-to-dielectric bonding and metal-to-metal bonding.