US 2024/0266323 A1 · STACKED SEMICONDUCTOR DIE ARCHITECTURE WITH MULTIPLE LAYERS OF DISAGGREGATION

Abstract

Stacked semiconductor die architectures having one or more base dies and techniques of forming such architectures are described. The stacked semiconductor die architectures may be included in or used to form semiconductor packages. A stacked semiconductor die architecture can include: (i) one or more base dies (e.g., at least one disaggregated base die, at least one monolithic base die, etc.); and (ii) a carrier wafer having multiple stacked semiconductor dies embedded in the carrier wafer, where the carrier wafer is on the one or more base dies and where one or more interconnect structures (e.g., wires, bumps, microbumps, pillars, etc.) couple the one or more base dies to the carrier wafer and/or the stacked semiconductor dies.

Claims20

Dependent claims

A stacked semiconductor architecture, comprising:

a first die and a second die;
and
a layer on the first die and the second die, the layer including a first plurality of dies entirely within a footprint of the first die and a second plurality of dies within a footprint of the second die, wherein the layer electrically couples the first die to the second die with first interconnect structures, and wherein one or more second interconnect structures couple one or more of the first plurality of dies or the second plurality of dies and one or more of the first die or the second die, the one or more second interconnect structures laterally adjacent to the first interconnect structures.

Dependencies are inferred from the claim text.

Stacked semiconductor die architecture with multiple layers of disaggregation

Life of this patent

Stacked semiconductor die architecture with multiple layers of disaggregation

Life of this patent

Abstract

Claims20