Bit retiring to mitigate bit errors

A memory system, comprising:

• one or more memory devices;
• and
• one or more controllers coupled with the one or more memory devices and configured to cause the memory system to;
• determine that a first set of bits retrieved from a first row of a memory array of the one or more memory devices includes one or more errors;
• remap a portion of the first row from a first row index to a second row index based at least in part on determining that the first set of bits includes the one or more errors, wherein the second row index, before remapping the first row, corresponds to a second row of the memory array;
• determine that a second set of bits retrieved from a third row of the memory array includes one or more errors, wherein the third row corresponds to a third row index;
• and
• select, for remapping a portion of the third row from the third row index based at least in part on determining that the second set of bits includes one or more errors, a fourth row index based at least in part on the fourth row index being subsequent to the second row index remapped to the portion of the first row, wherein the fourth row index, before remapping the third row, corresponds to a fourth row of the memory array.

A non-transitory computer-readable medium storing code comprising instructions which, when executed by processing circuitry of a memory system, cause the memory system to:

• determine that a first set of bits retrieved from a first row of a memory array includes one or more errors;
• remap a portion of the first row from a first row index to a second row index based at least in part on determining that the first set of bits includes the one or more errors, wherein the second row index, before remapping the first row, corresponds to a second row of the memory array;
• determine that a second set of bits retrieved from a third row of the memory array includes one or more errors, wherein the third row corresponds to a third row index;
• and
• select, for remapping a portion of the third row from the third row index based at least in part on determining that the second set of bits includes one or more errors, a fourth row index based at least in part on the fourth row index being subsequent to the second row index remapped to the portion of the first row, wherein the fourth row index, before remapping the third row, corresponds to a fourth row of the memory array.