Semiconductor memory structure

A memory cell, comprising:

• an active region;
• a first transistor including a source/drain region within the active region, wherein the source/drain region defines an individual bit line node;
• and
• a plurality of bit lines corresponding to the individual bit line node and electrically connected to the source/drain region using a plurality of conductive vias, wherein at least one of the plurality of conductive vias is disposed over the active region.

A memory circuit, comprising:

• a plurality of active regions, wherein each of the plurality of active regions is associated with a particular memory cell;
• and
• a plurality of bit lines associated with each of the plurality of active regions;
• wherein the plurality of bit lines associated with a given active region correspond to a same bit line node and are electrically connected to a same source/drain region of the given active region using a respective set of conductive vias coupled to the plurality of bit lines associated with the given active region.