Display substrate, display device, and manufacturing method of display substrate

A display device comprising a display substrate,

• wherein the display substrate comprises:
• a base substrate, and a gate driving circuit and a plurality of clock signal lines arranged on the base substrate,
• wherein the gate driving circuit comprises a plurality of shift register units,
• each shift register unit comprises an input circuit, a first control circuit, a second control circuit, an output circuit, a trigger terminal, and an output terminal,
• the input circuit is electrically connected with the trigger terminal and a first node respectively and receives a first control signal, and is configured to input a trigger signal received by the trigger terminal to the first node under control of the first control signal;
• the first control circuit is electrically connected with the first node, a second node, and a first output node respectively and receives the first control signal, a second control signal, and a third control signal, and is configured to write a first output control signal into the first output node under control of the first control signal, a voltage of the first node, and the second control signal, wherein the first output control signal comprises the third control signal;
• the second control circuit is electrically connected with the first node, the second node, and a second output node respectively and receives the second control signal, and is configured to write a second output control signal into the second output node under control of the second control signal and a voltage of the second node;
• the output circuit is electrically connected with a first voltage line, a second voltage line, the first output node, the second output node, and the output terminal respectively, and is configured to write a first voltage signal provided by the first voltage line or a second voltage signal provided by the second voltage line into the output terminal as an output signal under control of the first output control signal and the second output control signal;
• the plurality of clock signal lines comprise a first clock signal line, a second clock signal line, and a third clock signal line,
• the first clock signal line is configured to provide a first clock signal, the second clock signal line is configured to provide a second clock signal, and the third clock signal line is configured to provide a third clock signal,
• the plurality of shift register units comprise an n-th stage shift register unit, and n is a positive integer,
• an input circuit of the n-th stage shift register unit is connected with the first clock signal line to receive the first clock signal as the first control signal,
• a first control circuit of the n-th stage shift register unit is connected with the first clock signal line, the second clock signal line, and the third clock signal line to receive the first clock signal as the first control signal, to receive the second clock signal as the second control signal, and to receive the third clock signal as the third control signal,
• a second control circuit of the n-th stage shift register unit is connected with the second clock signal line to receive the second clock signal as the second control signal, and
• a phase of the second clock signal is opposite to a phase of the third clock signal.

A manufacturing method for manufacturing of a display substrate,

• wherein the display substrate comprises:
• a base substrate, and a gate driving circuit and a plurality of clock signal lines arranged on the base substrate,
• wherein the gate driving circuit comprises a plurality of shift register units,
• each shift register unit comprises an input circuit, a first control circuit, a second control circuit, an output circuit, a trigger terminal, and an output terminal,
• the input circuit is electrically connected with the trigger terminal and a first node respectively and receives a first control signal, and is configured to input a trigger signal received by the trigger terminal to the first node under control of the first control signal;
• the first control circuit is electrically connected with the first node, a second node, and a first output node respectively and receives the first control signal, a second control signal, and a third control signal, and is configured to write a first output control signal into the first output node under control of the first control signal, a voltage of the first node, and the second control signal, wherein the first output control signal comprises the third control signal;
• the second control circuit is electrically connected with the first node, the second node, and a second output node respectively and receives the second control signal, and is configured to write a second output control signal into the second output node under control of the second control signal and a voltage of the second node;
• the output circuit is electrically connected with a first voltage line, a second voltage line, the first output node, the second output node, and the output terminal respectively, and is configured to write a first voltage signal provided by the first voltage line or a second voltage signal provided by the second voltage line into the output terminal as an output signal under control of the first output control signal and the second output control signal;
• the plurality of clock signal lines comprise a first clock signal line, a second clock signal line, and a third clock signal line,
• the first clock signal line is configured to provide a first clock signal, the second clock signal line is configured to provide a second clock signal, and the third clock signal line is configured to provide a third clock signal,
• the plurality of shift register units comprise an n-th stage shift register unit, and n is a positive integer,
• an input circuit of the n-th stage shift register unit is connected with the first clock signal line to receive the first clock signal as the first control signal,
• a first control circuit of the n-th stage shift register unit is connected with the first clock signal line, the second clock signal line, and the third clock signal line to receive the first clock signal as the first control signal, to receive the second clock signal as the second control signal, and to receive the third clock signal as the third control signal,
• a second control circuit of the n-th stage shift register unit is connected with the second clock signal line to receive the second clock signal as the second control signal, and
• a phase of the second clock signal is opposite to a phase of the third clock signal;
• wherein the manufacturing method comprises:
• providing the base substrate;
• sequentially forming a semiconductor layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer, an oxide layer, a fourth insulating layer, a third metal layer, a fifth insulating layer, and a fourth metal layer in a direction perpendicular to the base substrate;
• wherein the plurality of clock signal lines are in the fourth metal layer;
• the gate driving circuit is formed in the semiconductor layer, the oxide layer, the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer;
• and
• the gate driving circuit is respectively connected with the plurality of clock signal lines through a plurality of holes located in the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer.