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US 2024/0264975 A1Published application
Reconfigurable Parallel Processing
AssigneeXDL Technologies Inc.
InventorsYuan Li, Jianbin Zhu
Life of this patent
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Abstract
Processors, systems and methods are provided for thread level parallel processing. A processor may comprise a plurality of processing elements (PEs) that each may comprise a configuration buffer, a sequencer coupled to the configuration buffer of each of the plurality of PEs and configured to distribute one or more PE configurations to the plurality of PEs, and a gasket memory coupled to the plurality of PEs and being configured to store at least one PE execution result to be used by at least one of the plurality of PEs during a next PE configuration.
Claims211
A processor, comprising:
- a plurality of processing elements (PEs) each comprising a configuration buffer;
- a sequencer coupled to the configuration buffer of each of the plurality of PEs and configured to distribute one or more PE configurations to the plurality of PEs;
- and
- a gasket memory coupled to the plurality of PEs and being configured to store at least one PE execution result to be used by at least one of the plurality of PEs during a next PE configuration.
1 more element
A method, comprising:
- mapping an execution kernel into a virtual data path at a processor, wherein the execution kernel includes a sequence of instructions to be executed by the processor, and the processor comprises various reconfigurable units that include a gasket memory;
- chopping the virtual data path into one or more physical data paths;
- delivering configurations to various reconfigurable units of the processor for the various reconfigurable units to form the one or more physical data paths to execute the sequence of instructions;
- and
- executing the processor to complete the one or more physical data paths by operating the various reconfigurable units according to the configurations, including routing data from one physical data path to the gasket memory to be used in a future physical data path as input.
2 more elements
A system, comprising:
- a processor, comprising:
- a sequencer configured to map an execution kernel to be executed by the processor into a virtual data path and chop the virtual data path into one or more physical data paths;
- a plurality of processing elements (PEs) coupled to the sequencer, each of the plurality of PEs comprising a configuration buffer configured to receive PE configurations for the one or more physical data paths from the sequencer;
- and
- a gasket memory coupled to the plurality of PEs and being configured to store data from one of the one or more physical data paths to be used by another physical data path of the one or more physical data paths as input.
2 more elements
A processor, comprising
- a plurality of processing elements (PEs);
- a plurality of switch boxes arranged in a plurality of columns, each of the plurality of switch boxes being associated with a respective PE and configured to provide input data switching for the respective PE;
- a plurality of memory ports arranged in the plurality of columns and being coupled to a memory unit and a top switch box in each column of the plurality of columns, each of the plurality of memory port being configured to provide data access to the memory unit for one or more switch boxes in a respective column;
- a plurality of inter-column switch boxes (ICSBs) each coupled to a bottom switch box in each column of the plurality of columns;
- and
- a gasket memory with its input coupled to a memory port, a PE, one or more switch boxes and an ICSB in a last column of the plurality of columns, and its output coupled to a memory port, one or more switch boxes and an ICSB in a first column of the plurality of columns.
3 more elements
A processor, comprising:
- a plurality of processing elements (PEs) each comprising a configuration buffer and a plurality of arithmetic logic units (ALUs), and each configured to operate independently according to respective PE configurations stored in the configuration buffer;
- and
- a gasket memory coupled to the plurality of PEs and being configured to store at least one PE execution result to be used by at least one of the plurality of PEs during a next PE configuration.
A processor, comprising:
- a plurality of processing elements (PEs) arranged in a plurality of columns;
- a plurality of switch boxes (SBs) each associated with a separate PE of the plurality of PEs to providing data switching;
- and
- a gasket memory coupled to the plurality of PEs and being configured to store at least one PE execution result to be delivered to at least one of the plurality of PEs via a switch box for the PE execute result to be used as input data during a next PE configuration.
1 more element
A method, comprising:
- mapping an execution kernel into a virtual data path, wherein the execution kernel includes a sequence of instructions to be executed by a processor, and the processor comprises various reconfigurable units that form repetitive columns;
- chopping the virtual data path into one or more physical data paths to fit each physical data path into the repetitive columns respectively;
- and
- delivering configurations to various reconfigurable units of the processor for the various reconfigurable units to form the one or more physical data paths to execute the sequence of instructions.
1 more element
A method, comprising:
- mapping an execution kernel into a virtual data path for a processor to execute, the processor comprising various reconfigurable units that form repetitive columns;
- chopping the virtual data path into a plurality of physical data paths including a first physical data path that fits into the repetitive columns and a second physical data path that fits into the repetitive columns;
- and
- delivering configurations to various reconfigurable units for the repetitive columns to form the first physical data path to execute a first part of the execution kernel and form the second physical data path to execute a second part of the execution kernel.
1 more element
A processor, comprising:
- a plurality of reconfigurable units including a plurality of processing elements (PEs) and a plurality of memory ports (MPs) for the plurality of PEs to access a memory unit, each of the plurality of reconfigurable units comprising a configuration buffer and a reconfiguration counter;
- and
- a sequencer coupled to the configuration buffer of each of the plurality of reconfigurable units and configured to distribute a plurality of configurations to the plurality of reconfigurable units for the plurality of PEs and the plurality of memory ports to execute a sequence of instructions.
A method, comprising:
- delivering a plurality of configurations to a plurality of reconfigurable units of a processor for the plurality of reconfigurable units to form a plurality of physical data paths to execute a sequence of instructions, each of the plurality of configurations including a specified number;
- repeating a respective operation at each of the plurality of reconfigurable units for the specified number of times, including executing a first instruction of the sequence of instructions at a first reconfigurable processing element (PE) the specified number of times according to a first configuration in a first physical data path;
- and
- reconfiguring each of the plurality of reconfiguration units to a new configuration after repeating the respective operation the specified number of times, including executing a second instruction of the sequence of instructions at the first reconfigurable PE the specified number of times according to a second configuration in a second physical data path.
1 more element
A method, comprising:
- delivering a first set of configurations to a plurality of reconfigurable units of a processor for the plurality of reconfigurable units to form a first physical data path to execute a first part of a sequence of instructions, each of the first set of configurations including a specified number;
- delivering a second set of configurations to the plurality of reconfigurable units for the plurality of reconfigurable units to form a second physical data path to execute a second part of a sequence of instructions, each of the second set of configurations including the specified number;
- applying the first set of configurations at the plurality of reconfigurable units for each of the plurality of reconfiguration units to repeat a respective operation the specified number of times to execute the first physical data path;
- storing data from the first physical data path to a gasket memory;
- and
- applying the second set of configurations at the plurality of reconfigurable units for each of the plurality of reconfiguration units to repeat a respective operation the specified number of times to execute the second physical data path, with the data stored in the gasket memory as input to the second physical data path.
3 more elements
A processor, comprising:
- a plurality of processing elements (PEs) each having a plurality of arithmetic logic units (ALUs) that are configured to execute a same instruction in parallel threads;
- and
- a plurality of memory ports (MPs) for the plurality of PEs to access a memory unit, each of the plurality of MPs comprising an address calculation unit configured to generate respective memory addresses for each thread to access a different memory bank in the memory unit.
A method, comprising:
- generating a plurality of memory addresses by an address calculation unit in a memory port of a plurality of memory ports, wherein the plurality of memory ports provide access to a memory unit for a plurality of processing elements (PEs) each having a plurality of arithmetic logic units (ALUs) that are configured to execute a same instruction in parallel threads;
- and
- accessing a plurality of memory banks in the memory unit using the plurality of memory addresses with each thread accessing a different memory bank in the memory unit.
A processor, comprising:
- a memory unit comprising a plurality of memory banks;
- a plurality of processing elements (PEs) each having a plurality of arithmetic logic units (ALUs) that are configured to execute a same instruction in parallel threads;
- and
- a plurality of memory ports (MPs) for the plurality of PEs to access the memory unit, each of the plurality of MPs comprising an address calculation unit configured to generate respective memory addresses for each thread to access a different memory bank in the memory unit.
1 more element
A processor, comprising:
- a processing element (PE) having a plurality of arithmetic logic units (ALUs) that are configured to execute a same instruction in parallel threads;
- and
- a memory port (MP) for the PE to access a memory unit, the MP comprising an address calculation unit configured to generate respective memory addresses for each thread to access a different memory bank in the memory unit.
A method, comprising:
- generating a plurality of memory addresses by an address calculation unit in a memory port, wherein the memory port provides access to a memory unit for a processing element (PE) having a plurality of arithmetic logic units (ALUs) configured to execute a same instruction in parallel threads;
- and
- accessing a plurality of memory banks in the memory unit using the plurality of memory addresses with each thread accessing a different memory bank in the memory unit.
A processor, comprising:
- a plurality of processing elements (PEs) each having a plurality of arithmetic logic units (ALUs) that are configured to execute a same instruction in parallel threads;
- and
- a plurality of memory ports (MPs) for the plurality of PEs to access a memory unit, each of the plurality of MPs comprising an address calculation unit configured to generate respective memory addresses for each thread to access a common area in the memory unit.
A method, comprising:
- generating a plurality of memory addresses by an address calculation unit in a memory port of a plurality of memory ports, wherein the plurality of memory ports provide access to a memory unit for a plurality of processing elements (PEs) each having a plurality of arithmetic logic units (ALUs) that are configured to execute a same instruction in parallel threads;
- and
- accessing a plurality of memory banks in the memory unit using the plurality of memory addresses with all threads accessing a common area in the memory unit.
A processor, comprising:
- a memory unit comprising a plurality of memory banks;
- a plurality of processing elements (PEs) each having a plurality of arithmetic logic units (ALUs) that are configured to execute a same instruction in parallel threads;
- and
- a plurality of memory ports (MPs) for the plurality of PEs to access the memory unit, each of the plurality of MPs comprising an address calculation unit configured to generate respective memory addresses for each thread to access a common area across the plurality of memory banks in the memory unit.
1 more element
A processor, comprising:
- a processing element (PE) having a plurality of arithmetic logic units (ALUs) that are configured to execute a same instruction in parallel threads;
- and
- a memory port (MP) for the PE to access a memory unit, the MP comprising an address calculation unit configured to generate respective memory addresses for each thread to access a common area in the memory unit.
A method, comprising:
- generating a plurality of memory addresses by an address calculation unit in a memory port, wherein the memory port provides access to a memory unit for a processing element (PE) having a plurality of arithmetic logic units (ALUs) configured to execute a same instruction in parallel threads;
- and
- accessing a plurality of memory banks in the memory unit using the plurality of memory addresses with each thread accessing a common area in the memory unit.
A processor, comprising:
- a plurality of processing elements (PEs) each comprising:
- an arithmetic logic unit (ALU);
- a data buffer associated with the ALU;
- and
- an indicator associated with the data buffer to indicate whether a piece of data inside the data buffer is to be reused for repeated execution of a same instruction as a pipeline stage.
2 more elements
A method, comprising:
- determining that a piece of data is to be shared and reused by all threads at a processing element (PE) of a processor during one configuration applied at the PE;
- loading the piece of data once into a data buffer of the PE;
- setting an indicator associated with the data buffer to indicate that the piece of data is to be reused;
- and
- executing a same instruction with the piece of data as an input at the PE repeatedly a number of times as a pipeline stage, the same instruction and the number being specified by the configuration.
2 more elements
A processor, comprising:
- a plurality of processing elements (PEs) each comprising:
- a vector arithmetic logic unit (ALU) including a plurality of ALUs;
- a plurality of data buffer associated with each of the plurality of ALU;
- and
- a plurality of indicators each associated with a separate data buffer to indicate whether a piece of data inside a respective data buffer is to be reused for repeated execution of a same instruction as a pipeline stage at a respective PE.
2 more elements
A method, comprising:
- receiving a first configuration and a second configuration at a reconfigurable unit of a processor, the reconfigurable unit having a configuration buffer to store the first configuration and the second configuration;
- executing a first operation a first number of times according to the first configuration, the first configuration being part of a first physical data path for executing a first part of a sequence of instructions;
- and
- reconfiguring the reconfigurable unit to execute a second operation a second number of times according to the second configuration, the second configuration being part of a second physical data path for executing a second part of a sequence of instructions.
1 more element
A method, comprising:
- executing a first instruction at a reconfigurable processing element a number of times according to a first configuration, the reconfigurable processing element being configured to be part of a first physical data path during the first configuration;
- delivering an execution result from the reconfigurable processing element to a gasket memory to temporality stored the execution result after each execution of the first instruction;
- and
- feeding the execution result stored in the gasket memory to a second physical data path.
1 more element
Dependencies are inferred from the claim text.