US 2024/0258428 A1Published application

Fin field-effect transistor device and method of forming the same

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsJian-Jou Lian, Chun-Neng Lin, Chieh-Wei Chen, Tzu-Ang Chiang, Ming-Hsi Yeh

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Abstract

A method of forming a semiconductor device includes surrounding a dummy gate disposed over a fin with a dielectric material; forming a gate trench in the dielectric material by removing the dummy gate and by removing upper portions of a first gate spacer disposed along sidewalls of the dummy gate, the gate trench comprising a lower trench between remaining lower portions of the first gate spacer and comprising an upper trench above the lower trench; forming a gate dielectric layer, a work function layer and a glue layer successively in the gate trench; removing the glue layer and the work function layer from the upper trench; filling the gate trench with a gate electrode material after the removing; and removing the gate electrode material from the upper trench, remaining portions of the gate electrode material forming a gate electrode.

Claims20

Dependent claims

A semiconductor device comprising:

a fin protruding above a substrate;
a first gate structure over the fin;
first gate spacers extending along sidewalls of the first gate structure;
and
second gate spacers extending along sidewalls of the first gate spacers, wherein the first gate spacers are between the first gate structure and the second gate spacers, wherein a second upper surface of the second gate spacers distal from the substrate extends further from the substrate than a first upper surface of the first gate spacers distal from the substrate, wherein the first gate structure comprises:
a first gate dielectric material extending along an upper surface of the fin and inner sidewalls of the first gate spacers facing the first gate structure;
a first work function layer over the first gate dielectric material;
a first capping layer over and contacting the first work function layer, wherein the first capping layer has a U-shaped cross-section, wherein the first capping layer contacts and extends along lower sidewalls of the first work function layer;
a first glue layer over and contacting the first capping layer, wherein the first glue layer contacts and extends along upper sidewalls of the first work function layer;
and
a first gate electrode embedded in the first glue layer.

8 more elements

A semiconductor device comprising:

a fin protruding above a substrate;
a first gate structure over the fin;
first gate spacers along sidewalls of the first gate structure;
and
second gate spacers along exterior sidewalls of the first gate spacers facing away from the first gate structure, wherein the second gate spacer extends further from the substrate than the first gate spacers, wherein the first gate structure comprises:
a first gate dielectric material along an upper surface of the fin and inner sidewalls of the first gate spacers facing the first gate structure;
a first work function layer over the first gate dielectric material;
a second work function layer over and contacting the first work function layer, wherein the second work function layer has a U-shaped cross-section, wherein the second work function layer contacts and extends along lower portions of sidewalls of the first work function layer;
a first capping layer filling a region between opposing sidewalls of the second work function layer;
a first glue layer over and contacting the first capping layer and the second work function layer, wherein the first glue layer contacts and extends along upper portions of the sidewalls of the first work function layer;
and
a first gate electrode embedded in the first glue layer.

9 more elements

A semiconductor device comprising:

a fin protruding above a substrate;
a first gate structure over the fin;
and
first plurality of gate spacers along sidewalls of the first gate structure, wherein the first plurality of gate spacers includes first gate spacers contacting the first gate structure, and second gate spacers contacting the first gate spacers, wherein the second gate spacers extend further from the substrate than the first gate spacers,
wherein the first gate structure comprises:
a first gate dielectric material along an upper surface of the fin and inner sidewalls of the first gate spacers facing the first gate structure;
a first work function layer over the first gate dielectric material;
a second work function layer over and contacting the first work function layer, wherein the second work function layer has a U-shaped cross-section, wherein the second work function layer contacts and extends along lower portions of sidewalls of the first work function layer;
a first glue layer over and contacting the second work function layer, wherein the first glue layer contacts and extends along upper portions of the sidewalls of the first work function layer, wherein the first glue layer fills a region between opposing sidewalls of the second work function layer;
and
a first gate electrode embedded in the first glue layer.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/630,549Filed 9 Apr 2024
Priority: 18 Oct 2019
Published: 1 Aug 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10D 30/62
Insulated-gate field-effect transistors [IGFET]: fin field-effect transistors [FinFET]
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 64/017
Manufacture or treatment: using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e.…
H10D 84/0184
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their gate sidewall spacers

Family

Application16/657,480Division · filed 18 Oct 2019
Application17/814,865Continuation · filed 26 Jul 2022
Application18/630,549Continuation
Application17/814,865Division
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US 2021/0119034 A1Published application
US 2022/0359741 A1Published application
US 2024/0258428 A1This patent

From the US filing history. Foreign family members aren’t listed.

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