Cross field effect transistor library cell architecture design

A method comprising:

• forming, in a first cell of an integrated circuit, a first pair of transistors with channels of different doping polarities configured to receive a first input signal by each transistor of the first pair of transistors;
• forming, in the first cell, a second pair of transistors with channels of different doping polarities configured to receive two different input signals, wherein a transistor of a first doping polarity of the second pair of transistors has a greater length of a gate region than a transistor of the second doping polarity of the first pair of transistors;
• and
• responsive to a potential being applied to an input node of the integrated circuit, conveying a current from the input node to an output node of the integrated circuit through the first cell.

A integrated circuit comprising:

• a first cell comprising:
• a first pair of transistors with channels of different doping polarities configured to receive a first input signal by each transistor of the first pair of transistors;
• a second pair of transistors with channels of different doping polarities configured to receive two different input signals, wherein a transistor of a first doping polarity of the second pair of transistors has a greater length of a gate region than a transistor of the second doping polarity of the first pair of transistors;
• and
• wherein responsive to a potential being applied to an input node, the integrated circuit conveys a current from the input node to an output node of the integrated circuit through the first cell.

A system comprising:

• a memory configured to store instructions;
• an integrated circuit configured to execute the stored instructions, wherein the integrated circuit comprises:
• a first pair of transistors with channels of different doping polarities configured to receive a first input signal by each transistor of the first pair of transistors;
• a second pair of transistors with channels of different doping polarities configured to receive two different input signals, wherein a transistor of a first doping polarity of the second pair of transistors has a greater length of a gate region than a transistor of the second doping polarity of the first pair of transistors;
• and
• wherein responsive to a potential being applied to an input node, the integrated circuit conveys a current from the input node to an output node of the integrated circuit through the first cell.