US 2024/0258278 A1Published application

Semiconductor package including stacked semiconductor chips

AssigneeSamsung Electronics Co., Ltd.

InventorsHyungchul SHIN, Won IL LEE, Hyuekjae LEE, Enbin JO

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Abstract

A semiconductor package includes a lower semiconductor chip, a first semiconductor chip, a first through-electrode vertically penetrating the first semiconductor substrate, a first upper pad connected to the first through electrode, a first circuit layer disposed on the lower surface of the first semiconductor substrate, and a first lower pad disposed on a lower surface of the first circuit layer. A second semiconductor chip includes a second through-electrode spaced apart from the first through-electrode and vertically penetrating the second semiconductor substrate. A second upper pad is connected to the second through electrode. A second circuit layer is disposed on the lower surface of the second semiconductor substrate, and a second lower pad is connected to the second through-electrode on the lower surface of the second circuit layer through the second circuit layer and is integrally formed with the first upper pad.

Claims20

Dependent claims

A semiconductor package, comprising:

a lower semiconductor chip;
a first semiconductor chip stacked on the lower semiconductor chip;
and
a second semiconductor chip stacked on the lower semiconductor chip,
wherein the first semiconductor chip includes:
a first semiconductor substrate;
a first through electrode vertically penetrating the first semiconductor substrate;
a first upper pad electrically connected to the first through electrode on an upper surface of the first semiconductor substrate;
an upper protective layer at least partially surrounding the first upper pad on the upper surface of the first semiconductor substrate;
a first circuit layer disposed on a lower surface of the first semiconductor substrate;
and
a first lower pad connected to the first through electrode through the first circuit layer on a lower surface of the first circuit layer,
wherein the second semiconductor chip includes:
a second semiconductor substrate;
a second through electrode vertically penetrating the second semiconductor substrate;
a second upper pad electrically connected to the second through electrode on an upper surface of the second semiconductor substrate;
a second circuit layer disposed on a lower surface of the second semiconductor substrate;
a second lower pad electrically connected to the second through electrode through the second circuit layer on a lower surface of the second circuit layer;
and
a lower protective layer at least partially surrounding the second lower pad on the lower surface of the second circuit layer,
wherein the lower protective layer is in direct contact with the upper protective layer,
wherein the second lower pad is in contact with the first upper pad and forms an integral body therewith, and
wherein the first through electrode is horizontally spaced apart from the second through electrode, in a plan view.

20 more elements

Dependencies are inferred from the claim text.