Loading patent…
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChih-Yuan TING, Ya-Lien LEE, Chung-Wen WU, Jeng-Shiou CHEN
Estimating the term…
One or more techniques or systems for mitigating pattern collapse are provided herein. For example, a semiconductor structure for mitigating pattern collapse is formed. In some embodiments, the semiconductor structure includes an extreme low-k (ELK) dielectric region associated with a via or a metal line. For example, a first metal line portion and a second metal line portion are associated with a first lateral location and a second lateral location, respectively. In some embodiments, the first portion is formed based on a first stage of patterning and the second portion is formed based on a second stage of patterning. In this manner, pattern collapse associated with the semiconductor structure is mitigated, for example.
A semiconductor structure for mitigating pattern collapse, comprising:
A semiconductor structure for mitigating pattern collapse, comprising:
A semiconductor structure for mitigating pattern collapse, comprising:
Dependencies are inferred from the claim text.