Command address control circuit, and semiconductor apparatus and semiconductor system including the command address control circuit

A command address control circuit comprising:

• a command decoding circuit configured to receive a command address signal set in synchronization with a first reference clock signal and to generate a command detection signal by detecting a type of command address signal set based on some command address signals of the command address signal set;
• an error decision circuit configured to generate an error detection signal by detecting whether an error is present in the command address signal set in synchronization with the first reference clock signal and a second reference clock signal and to generate a first block signal and a second block signal based on the error detection signal and the command detection signal;
• a first shifting circuit configured to generate some internal command address signals of an internal command address signal set by shifting some command address signals of the command address signal set based on the first reference clock signal, the first block signal, and the second block signal;
• and
• a second shifting circuit configured to generate remaining internal command address signals of the internal command address signal set by shifting remaining command address signals of the command address signal set based on the second reference clock signal.

A command address control circuit comprising:

• a pipe control circuit configured to generate an input control signal and an output control signal based on a reference clock signal;
• a command decoding circuit configured to generate a command detection signal by detecting a type of command address signal set based on the command address signal set;
• a parity check circuit configured to generate an error detection signal by detecting whether an error is present in the command address signal set;
• a reset control circuit configured to generate a reset signal, based on the reference clock signal, the error detection signal, and the command detection signal;
• and
• a pipe circuit configured to store the command address signal set based on the input control signal, to output the stored command address signal set as an internal command address signal set based on the output control signal, and to invalidate the stored command address signal set based on the reset signal.