Phase-change memory cell and method for fabricating the same

A phase-change memory (PCM) cell comprising a first electrode, a second electrode, and a phase-change feature disposed between the first electrode and the second electrode,

• wherein the PCM cell is configured to switch between multiple data states based on a write operation performed on the PCM cell;
• wherein the write operation includes a reset stage, and a set stage following the reset stage;
• wherein, in the set stage, a plurality of set current pulses are applied to the PCM cell;
• and
• wherein a relationship between a cell resistance of the PCM cell and current amplitudes of the set current pulses form a curve that has a slope section with a slope of n, where 2≤n≤5, and n is obtained by using an equation of RSET=C0×ISET−n+C1 to approximate the slope section, where ISET represents the current amplitudes of the set current pulses in μA, RSET represents the cell resistance in kΩ, which results from the set current pulses, and C0 and C1 are constants.

A phase-change memory (PCM) cell, comprising a first electrode, a second electrode, and a phase-change feature that is disposed between the first electrode and the second electrode, wherein the phase-change feature is configured to switch between multiple data states based on a write operation performed on the PCM cell;

• wherein the write operation includes a reset stage in which a plurality of reset current pulses are applied to the PCM cell through the first electrode and the second electrode, and a set stage which follows the reset stage and in which a plurality of set current pulses are applied to the PCM cell through the first electrode and the second electrode;
• wherein current amplitudes of the set current pulses correspond to at least two different predetermined reset current amplitudes, and monotonically increase over time;
• wherein the set stage includes multiple sub-stages that occur sequentially;
• wherein at least two of the sub-stages correspond to different pulse widths;
• and
• wherein each of the sub-stages includes at least two of the set current pulses, and said at least two of the set current pulses have a same pulse width.