Method and system for verifying integrated circuit

A system for verifying an integrated circuit, the system comprising:

• at least one processor;
• and
• a non-transitory storage medium storing instructions which, when executed by the at least one processor, cause the system to execute a process of verifying the integrated circuit,
• wherein the at least one processor is configured to obtain first data defining elements in the integrated circuit, and second data defining positions and connection relationships of the elements,
• generate chip data by merging the first data and the second data in background,
• perform at least one physical verification in parallel, and
• generate output data, based on results of the at least one physical verification,
• wherein the performing of at least one physical verification in parallel includes,
• extracting verification input data used for physical verification from the chip data.

A non-transitory storage medium for storing instructions which, when executed by at least one processor, cause the at least one processor to execute a process of verifying an integrated circuit,

• wherein the process of verifying the integrated circuit comprises,
• obtaining first data defining elements in the integrated circuit, and second data defining positions and connection relationships of the elements;
• generating chip data by merging the first data and the second data in background;
• performing at least one physical verification in parallel;
• and
• generating output data, based on results of the at least one physical verification,
• wherein the performing of at least one physical verification in parallel comprises
• extracting verification input data used for physical verification from the chip data.