US 2024/0256748 A1Published application

Synchonous fifo

AssigneeSuzhou Metabrain Intelligent Technology Co., Ltd.

InventorsHongliang WANG, Deshan ZHANG, Qi MOU

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Abstract

Provided is a synchronous FIFO, including a data storage circuit, a first logic circuit, a second logic circuit and indication circuits. The data storage circuit includes N first registers, N first multiplexers and N first deciders, where N is a positive integer; and the N first registers and the N first multiplexers are alternately connected. Based on the registers, the synchronous FIFO builds a storage required by the FIFO, and primarily includes the registers, the multiplexers and the deciders, the use of an RAM is avoided, that is, there is no need to occupy the RAM, and there is no need to perform RAM read-write enabling and address control, thereby avoiding wasting RAM resources. In designs with lower storage depth requirements, few resources are occupied, so that a chip area is greatly reduced, the cost is reduced, and layout and wiring are more convenient.

Claims20

Dependent claims

A synchronous First Input First Output (FIFO), comprising:

a data storage circuit, a first logic circuit, a second logic circuit and indication circuits, wherein the data storage circuit comprises N first registers, N first multiplexers and N first deciders, where N is a positive integer;
the N first registers and the N first multiplexers are alternately connected;
the N first deciders are in one-to-one correspondence with the N first multiplexers;
and the indication circuits are in one-to-one correspondence with the N first registers;
the first register is configured to store data;
the first decider is configured to output a first control signal to the corresponding first multiplexer according to a state value of the first register connected with the corresponding first multiplexer;
the first multiplexer is configured to output, according to the first control signal, data output by an output end of the first register connected with the first multiplexer or data input by a data input end of the synchronous FIFO to an input end of the first register connected with the first multiplexer;
the first logic circuit is configured to obtain a read flag signal according to an empty flag output signal of the synchronous FIFO and a read signal input to the synchronous FIFO;
the second logic circuit is configured to obtain a write flag signal according to a full flag output signal of the synchronous FIFO and a write signal input to the synchronous FIFO;
and
the indication circuit is configured to obtain the state value of the corresponding first register according to the read flag signal and the write flag signal.

8 more elements

Dependencies are inferred from the claim text.