Accessing network chip resources
AssigneeArista Networks, Inc.
InventorsLakshmikanth Chowdary Pothula, Christopher Patrick Hayden
Life of this patent
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Abstract
A data processing system can include a first processor, a second processor, and one or more data storage resources each configured to store data for processing network traffic. The second processor can help the first processor perform direct memory access (DMA) operations to write the data into the one or more data storage resources using DMA channels. DMA channels may be allocated between the data storage resources based on the allocation of data for storage on different data storage resources.
Claims20
A method of data storage resource access on a network device, the method comprising:
- receiving an indication of how network traffic processor data is distributed across a plurality of data storage resources;
- and
- connecting a set of direct memory access channels to the plurality of data storage resources based on the received indication, wherein a given data storage resource in the plurality of data storage resources is coupled to multiple direct memory access channels in the set of direct memory access channels.
A network device comprising:
- processing circuitry having a command buffer that receives and buffers commands and a plurality of parallel command queues coupled to the command buffer;
- a plurality of data storage resources, wherein each command queue in the plurality of command queues stores commands for a different data storage resource in the plurality of data storage resources;
- and
- a set of direct memory access channels, wherein the processing circuitry performs the commands by writing network traffic processor data into the plurality data storage resources using the set of direct memory access channels.
A host system comprising:
- a host processor that includes a set of command storage structures each storing commands for a set of host processes executing on the host processor, and an additional command storage structure that receives and aggregates the commands from each command storage structure in set of command storage structures;
- a coprocessor having a command buffer that receive the aggregated commands from the additional command storage structure;
- and
- a plurality of data storage resources, wherein the coprocessor performs the commands by writing network traffic processor data into the plurality data storage resources using direct memory access channels.
Dependencies are inferred from the claim text.