Hardware accelerator for computing an algebraic function

A multi-thread processor for computing a function requiring only modular multiplications and modular additions, the processor comprising:

• a constants memory for storing a plurality of constants,
• a data memory for storing a plurality of multi-bit elements,
• a multiplier having a pair of inputs each for receiving respective first and second multiplier operands and producing a product of the first and second multiplier operands at an output of the multiplier,
• an adder having a pair of inputs each for receiving respective first and second adder operands and producing a sum of the first and second adder operands at an output of the adder, wherein the product of the first and second multiplier operands serves as the first adder operand,
• an accumulator memory having an input coupled to the output of the adder for storing a sum of the adder operands, and
• a program memory storing multiple instruction sets, each for execution on a successive clock, and each instruction set including instructions for defining respective addresses in said memories from which constants, elements and sums are to be accessed,
• a scheduler coupled to the program memory and configured to maintain a schedule of multiple threads executable by the processor in parallel, said schedule indicating for each of said threads whether the thread is available or idle, and the scheduler being configured on each successive clock to cycle through the threads and initiate a first available thread,
• a first selector responsive to instructions received from the program memory for selecting as the first multiplier operand for each thread a specified element from the data memory or the product of the first and second multiplier operands,
• a second selector responsive to instructions received from the program memory for selecting as the second multiplier operand for each thread a specified element from the data memory or a constant accessed from the constants memory or the product of the first and second multiplier operands, and
• a third selector responsive to instructions received from the program memory for selecting as the second adder operand for each thread either a sum stored in the accumulator memory or a constant stored in the constants memory.