High speed ripple adder

A method for reducing delay associated with processing a plurality of multi-bit numbers is a plurality of logic stages, each having plural signal inputs and a carry input for logically proceeding applied signals within a processing delay interval to produce an output representing selected significant bits of multi-bit numbers, and a carry output representing a logic overflow of the logically-processed applied signals, the method comprising:

• latching a plurality of multiple bit signals representative of multiple-bit numbers for selective application when clocked to a corresponding logic stage;
• prior to clocking to the logic stage or prior to processing by the logic stage, inverting at least one of the multiple bit signals;
• supplying a carry output from a logic stage to a carry input of a successive logic stage following a processing delay interval, wherein at least one carry output is inverted in relation to the carry input due to omission of an inverting function in a carry circuit of at least one logic stage;
• and
• selectively delaying substantially by the processing delay interval the clocking of the latched multiple bit signals to the logic stages to successively delay logic processing of the applied signals to produce associated output and carry output within a processing delay interval in each logic stage, wherein at delaying is reduced due to the omission of an inverting function in a carry circuit of at least one logic stage.

A logic circuit having reduced delay comprising:

• a plurality of input registers, each having a clock input configured to receive a clock signal and having an input connected to receive input signals and being operable in response to the clock signal applied thereto to output the input signals into a corresponding logic stage;
• a plurality of logic stages, each having plural signal inputs and a carry input for logically processing applied signals within a processing delay interval to produce an output representing selected significant bits of multi-bit numbers, and a carry output representing a logic overflow of the logically-processed applied signals, wherein for at least one of the plurality of logic stages the input signals are inverted prior to receipt at the logic stage or by the logic stage, prior to processing by the logic stage;
• a carry circuit within the logic stages, the carry circuit generating the carry output, such that for at least one logic stage the carry output is inverted as compared to the carry input;
• a plurality of output registers, each having a clock input and having an input connected to receive an output from a corresponding logic stage and being operable in response to a clock signal applied thereto to latch the output of the corresponding logic stage;
• and
• a delay element, having a reduced delay due to inverted output of the carry circuit, connected between clock inputs of each of the input registers and output registers to successively delay application of clock signals to the clock inputs of successively-oriented output registers for latching therein selected bits of a multiple-bit number.

A method for processing a plurality of multi-bit numbers in a plurality of logic stages, each having plural signal inputs and a carry input for logically processing applied signals within a processing delay interval to produce an output representing selected significant bits of multi-bit numbers, and a carry output representing a logic overflow of the logically-processed applied signals, the method comprising the steps of:

• latching a plurality of multiple bit signals representative of multiple-bit numbers for selective application when clocked to a corresponding logic stage;
• processing the multiple bit signals with the corresponding logic stage, such that at least one of the multiple bit signals are inverted prior to processing by the corresponding logic stage;
• latching the output of each logic stage for selective access when clocked;
• supplying a carry output from a logic stage to a carry input of a successive logic stage following a processing delay interval, wherein at least one carry input or carry output is inverted due to the logic stage carry circuit providing a carry output which is an inverted version the carry input;
• and
• successively delaying the clocking of access to each latched logic stage output substantially by the processing delay interval to accumulate latched outputs representative of a multiple bit number after a plural number of processing delay intervals.