Low resistance crosspoint architecture

A memory device prepared by a process comprising the steps of:

• etching through a first area of a layered assembly to form a gap in the layered assembly, wherein the layered assembly comprises a first layer comprising an electrode material, a second layer comprising a memory material, a third layer comprising a thermal barrier material, and a fourth layer comprising a first conductive material;
• depositing a dielectric material within the gap in the layered assembly;
• etching one or more holes through the dielectric material;
• depositing a second conductive material to form conductive vias in the one or more holes;
• and
• depositing a fifth layer comprising the first conductive material over the layered assembly, a portion of the fifth layer in contact with a conductive via and at least part of the fourth layer.

A method, comprising:

• etching through a first area of a layered assembly to form a gap in the layered assembly, wherein the layered assembly comprises a first layer comprising an electrode material, a second layer comprising a memory material, a third layer comprising a thermal barrier material, and a fourth layer comprising a first conductive material;
• depositing a dielectric material within the gap in the layered assembly;
• etching one or more holes through the dielectric material;
• depositing a second conductive material to form conductive vias in the one or more holes;
• and
• depositing a fifth layer comprising the first conductive material over the layered assembly, wherein the fifth layer is in contact with a conductive via and at least part of the fourth layer.

A method, comprising:

• forming a gap in a layered assembly, wherein the layered assembly comprises a first layer comprising an electrode material, a second layer comprising a memory material, a third layer comprising a thermal barrier material, and a fourth layer comprising a first conductive material;
• depositing a dielectric material within the gap in the layered assembly;
• etching one or more holes through the dielectric material;
• depositing a second conductive material to form conductive vias in the one or more holes;
• and
• depositing a fifth layer comprising the first conductive material over the layered assembly, a portion of the fifth layer in contact with a conductive via and at least part of the fourth layer.