Display panel
AssigneeLG Display Co., Ltd.
InventorJaeyi CHOI
Life of this patent
Estimating the term…
Abstract
A display panel according to embodiments of the disclosure may comprise a substrate in which a display area and a non-display area are divided, a gate driving circuit disposed on the substrate and disposed in a gate driving circuit area within the non-display area, a plurality of gate clock lines disposed on the substrate and disposed in a first line area positioned outside the gate driving circuit area in the non-display area, an overcoat layer disposed on the plurality of gate clock lines and the gate driving circuit, a cathode electrode disposed in the display area and extending to the non-display area, and a load deviation compensation pattern overlapping the plurality of gate clock lines.
Claims25
A display panel, comprising:
- a substrate having a display area and a non-display area;
- a gate driving circuit disposed on the substrate in a gate driving circuit area within the non-display area;
- a plurality of gate clock lines disposed on the substrate in a first line area positioned outside the gate driving circuit area in the non-display area;
- an overcoat layer disposed on the plurality of gate clock lines and the gate driving circuit;
- a cathode electrode disposed in the display area and in the non-display area;
- and
- a load deviation compensation pattern disposed in the non-display area and overlapping the plurality of gate clock lines.
A display panel, comprising:
- a substrate having a display area and a non-display area;
- a cathode electrode disposed in the display area and in the non-display area;
- a gate driving circuit disposed on the substrate in a gate driving circuit area within the non-display area;
- a plurality of gate clock lines disposed on the substrate in a first line area positioned outside the gate driving circuit area in the non-display area, and disposed to not overlap the cathode electrode in the non-display area;
- and
- an overcoat layer disposed on the plurality of gate clock lines and the gate driving circuit.
A display panel, comprising:
- a substrate having a display area and a non-display area;
- a cathode electrode disposed in the display area and in the non-display area;
- a gate driving circuit disposed on the substrate in a gate driving circuit area within the non-display area;
- a plurality of gate clock lines and a first level gate voltage line disposed on the substrate in a first line area positioned outside the gate driving circuit area in the non-display area, and disposed to not overlap the cathode electrode in the non-display area;
- a second level gate voltage line disposed on the substrate in a second line area positioned outside the gate driving circuit area in the non-display area, and located in position to be overlapped by the cathode electrode in the non-display area;
- a light emitting layer disposed in the non-display area and positioned between the cathode electrode and the second level gate voltage line in the second line area;
- and
- an overcoat layer disposed on the plurality of gate clock lines and the gate driving circuit.
Dependencies are inferred from the claim text.