Structure and formation method of package with integrated chips

A package structure, comprising:

• a logic control chip structure, wherein the logic control chip structure has a plurality of first transistors with a first average gate width;
• and
• a memory array cube directly bonded to the logic control chip structure through dielectric-to-dielectric bonding and metal-to-metal bonding, wherein the memory array cube has a plurality of second transistors with a second average gate width, and the second average gate width is wider than the first average gate width.

A method for forming a package structure, comprising:

• bonding a first memory-containing chip structure to a second memory-containing chip structure through dielectric-to-dielectric bonding and metal-to-metal bonding;
• and
• bonding a logic control chip structure to the second memory-containing chip structure through dielectric-to-dielectric bonding and metal-to-metal bonding, wherein the logic control chip structure is formed using a more advanced technology node than the second memory-containing chip structure.