High-voltage transistor with thin high-k metal gate and method of fabrication thereof

A memory device, comprising:

• a plurality of split gate transistors in a memory region, wherein each split gate transistor includes a memory gate stack disposed adjacent to a select gate stack;
• a plurality of logic transistors in a peripheral region, wherein at least one of the logic transistor includes a first high-K metal-gate (HKMG) stack;
• and
• a plurality of high voltage (HV) transistors in the peripheral region, wherein at least one of the HV transistor includes a second HKMG stack;
• wherein the memory and select gate stacks of the plurality of split gate transistors, the first HKMG stacks of the plurality of logic transistors and the second HKMG stacks of the plurality of HV transistors have a substantially same height, and wherein the memory and peripheral regions are disposed within a single substrate including a substantially flat and co-planar top surface.