Non-volatile memory device

A non-volatile memory device comprising:

• a memory cell array including a first word line, a second word line stacked on the first word line, a third word line stacked on the second word line, and a fourth word line stacked on the third word line;
• and
• first to fourth vertical pass transistors respectively connected to the first word line to the fourth word line,
• wherein two or more of the first to fourth vertical pass transistors share one drain of an active region.

An electronic system comprising:

• a main substrate;
• a non-volatile memory device on the main substrate;
• and
• a controller electrically connected to the non-volatile memory device on the main substrate,
• wherein the non-volatile memory device includes:
• a first semiconductor layer including a memory cell array including a plurality of word lines stacked in a vertical direction and a common source line below the plurality of word lines, a row decoder, and a plurality of vertical pass transistors connected between the plurality of word lines and the row decoder;
• and
• a second semiconductor layer including a page buffer connected to the memory cell array, and below the first semiconductor layer in the vertical direction, the plurality of vertical pass transistors sharing a drain of an active region and sharing a main contact, the main contact applying a signal to the active region.