Semiconductor device

A semiconductor device comprising:

• a first structure including circuit elements;
• and
• a second structure on the first structure and overlapping the first structure in a vertical direction,
• wherein the second structure includes:
• a stack structure including gate layers and interlayer insulating layers alternately stacked in the vertical direction;
• a first pattern layer between the first structure and the stack structure and spaced apart from the gate layers;
• a vertical memory structure penetrating through the stack structure in the vertical direction;
• a bit line on the stack structure and the vertical memory structure;
• and
• a contact plug between the bit line and the vertical memory structure,
• wherein the vertical memory structure includes:
• a core region;
• a channel layer on a side surface of the core region;
• and
• a data storage structure on an outer side surface of the channel layer,
• wherein the first pattern layer includes:
• a first pattern portion overlapping the gate layers in the vertical direction;
• and
• a second pattern portion extending form the first pattern portion in a direction away from the first structure and contacting the channel layer,
• wherein the gate layers include a first gate layer closest to the first structure and a second gate layer furthest from the first structure, and
• wherein a distance between the first structure and an upper end of the second pattern portion is greater than a distance between the first structure and the first gate layer.

A semiconductor device comprising:

• a first structure including circuit elements;
• and
• a second structure on the first structure,
• wherein the second structure includes:
• a stack structure including gate layers and interlayer insulating layers alternately stacked in a vertical direction;
• a pattern structure between the first structure and the stack structure and spaced apart from the gate layers;
• a vertical memory structure penetrating through the stack structure in the vertical direction;
• a bit line on the stack structure and the vertical memory structure;
• and
• a contact plug between the bit line and the vertical memory structure,
• wherein the vertical memory structure includes:
• a core region;
• a channel layer on a side surface of the core region;
• a data storage structure on an outer side surface of the channel layer;
• and
• a pad pattern on an upper surface of the core region,
• wherein the channel layer has an upper end contacting the pad pattern and a lower end opposite to the upper end,
• wherein the gate layers include a first gate layer closest to the first structure, a second gate layer closest to the bit line, and a third gate layer below the second gate layer,
• wherein the upper end of the channel layer is at a lower level than an upper surface of the second gate layer, and
• wherein a side surface of the pad pattern does not overlap an upper surface of the third gate layer in the vertical direction.