Memory device and fabrication method thereof

A memory device having a contact area and a core area next to each other along a first direction, and comprising:

• a plurality of first dielectric layers stacked in a second direction approximately perpendicular to the first direction and extending across the contact area and the core area;
• a plurality of second dielectric layers in a contact region in the contact area, each of the plurality of second dielectric layers being sandwiched between adjacent two of the plurality of first dielectric layers;
• and
• a plurality of conductor layers in the core area and in a protection region in the contact area, the protection region surrounding the contact region, and each of the plurality of conductor layers being sandwiched between adjacent two of the plurality of first dielectric layers and being co-layered with one of the plurality of second dielectric layers.

A memory system comprising:

• a memory device having a contact area and a core area next to each other along a first direction, and including:
• a plurality of first dielectric layers stacked in a second direction approximately perpendicular to the first direction and extending across the contact area and the core area;
• a plurality of second dielectric layers in a contact region in the contact area, each of the plurality of second dielectric layers being sandwiched between adjacent two of the plurality of first dielectric layers;
• and
• a plurality of conductor layers in the core area and in a protection region in the contact area, the protection region surrounding the contact region, and each of the plurality of conductor layers being sandwiched between adjacent two of the plurality of first dielectric layers and being co-layered with one of the plurality of second dielectric layers;
• and
• a memory controller configured to control operation of the memory device.